---
# System prepended metadata

title: Lab8_CS22B057

---

# Lab 8
Name: SHIVADHARSHAN S
Roll No.: CS22B057

---
## Question 1

**HalfAdder:**

```verilog=
module halfadder(a,b,s,c);
    input a,b;
    output s,c;
    xor(s,a,b);
    and(c,a,b);
endmodule
```

**FullAdder:**

```verilog=
module fulladder(a,b,cin,s,cout);
    input a,b,cin;
    output s,cout;
    wire w1,w2,w3;
    halfadder h1(a,b,w1,w2);
    halfadder h2(cin,w1,s,w3);
    assign cout = w2|w3;
    
endmodule
```
___

**TestBench:**

```verilog=
module fulladder_bench();
reg a1,b1,c1;
wire s,co;

    fulladder fulladder(a1,b1,c1,s,co);
    
    initial
        begin
        $monitor("a=%b,b=%b,cin=%b,co=%b,s=%b",a1,b1,c1,co,s);
	        a1=1'b0;b1=1'b0;c1='b0;
        #100	a1=1'b0;b1=1'b0;c1='b1;
        #100	a1=1'b0;b1=1'b1;c1='b0;
        #100	a1=1'b0;b1=1'b1;c1='b1;
        #100	a1=1'b1;b1=1'b0;c1='b0;
        #100	a1=1'b1;b1=1'b0;c1='b1;
        #100	a1=1'b1;b1=1'b1;c1='b0;
        #100	a1=1'b1;b1=1'b1;c1='b1;

end 
endmodule	
```
**Output:**
![Testbench for q1](https://hackmd.io/_uploads/HkKz1NlkR.png)

___

## Question 2

**4-bit Ripple Carry Adder:**

```verilog=
module rippleadder(a,b,s,carry_out);
parameter n=4;
input [n-1:0] a;
input [n-1:0]b;
output [n-1:0] s;
output carry_out;
wire [n-1:0] c;
genvar i;
generate
    for (i = 0 ;i<n ;i=i+1 ) 
        begin
        if (i==0) begin
            halfadder f(a[0],b[0],s[0],c[0]);
        end
        else begin
            fulladder f(a[i],b[i],c[i-1],s[i],c[i]);
        end
        end
        assign carry_out = c[n-1];
    
endgenerate
endmodule
```
**TestBench:**

```verilog=
module rippleadder_bench();
parameter n=4;
reg [n-1:0] a1;
reg [n-1:0] b1;
wire [n-1:0] s;
wire co;

rippleadder gate(a1,b1,s,co);

initial
begin
     $monitor("a=%b,b=%b,co=%b,s=%b",a1,b1,co,s);
	a1[3]=1'b0;a1[2]=1'b1;a1[1]=1'b1;a1[0]=1'b0;
        b1[3]=1'b0;b1[2]=1'b0;b1[1]=1'b1;b1[0]=1'b0;
#100	a1[3]=1'b1;a1[2]=1'b1;a1[1]=1'b1;a1[0]=1'b1;
        b1[3]=1'b0;b1[2]=1'b0;b1[1]=1'b0;b1[0]=1'b1;

end 
endmodule
```

**Output:**
![Testbench for q2](https://hackmd.io/_uploads/HJoQWVgJ0.png)
___

## Question 3

**2-1 multiplexer:**
```verilog=
module multiplexer(i1,i2,s0,y);
    input s0;
    input i1,i2;
    output y;
    wire y1,y2,y3;
    not(y3,s0);
    and(y2,i2,s0);
    and(y1,i1,y3);
    or(y,y1,y2);
endmodule
```

**Testbench:**
```verilog=
module multiplexer_tb();
    reg a,b,s;
    wire y;
    multiplexer mux(a,b,s,y);
    
    initial 
        begin
            $monitor("a=%b,b=%b,s=%b,y=%b",a,b,s,y);
            a=1'b0;b=1'b0;s='b0;
        #100	a=1'b0;b=1'b0;s='b1;
        #100	a=1'b0;b=1'b1;s='b0;
        #100	a=1'b0;b=1'b1;s='b1;
        #100	a=1'b1;b=1'b0;s='b0;
        #100	a=1'b1;b=1'b0;s='b1;
        #100	a=1'b1;b=1'b1;s='b0;
        #100	a=1'b1;b=1'b1;s='b1;
        end
endmodule
```
**Output:**
![Testbench for q3](https://hackmd.io/_uploads/r1OhGNx1A.png)
