# Lab 08
Name: CHATSE SIDDHANT MADHUKAR
Roll No.: CS22B016

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## Question 1
**Verilog Code - Half Adder**

module halfadder(a,b,s,c);
    input a,b;
    output s,c;
    assign s = a^b;
    assign c = a&b;
endmodule

**Verilog Code - Full adder using Half Adder**

module fulladder(a,b,c_in,s,c_out);
    input a,b,c_in;
    output s,c_out;
    wire w1,w2,w3;
    halfadder h1(a,b,w1,w2);
    halfadder h2(w1,c_in,s,w3);
    assign c_out = w2|w3;
endmodule

**Verilog Code - TestBench**

module fulladder_bench();
    reg a,b,c_in;
    wire s;
    wire c_out;
    fulladder f(a,b,c_in,s,c_out);
    initial
    begin
        $monitor("a=%b,b=%b,c_in=%b,s=%b,c_out=%b",a,b,c_in,s,c_out);
                a=1'b0;b=1'b0;c_in=1'b0;
        #100	a=1'b0;b=1'b0;c_in=1'b1;
        #100	a=1'b0;b=1'b1;c_in=1'b0;
        #100	a=1'b0;b=1'b1;c_in=1'b1;
        #100	a=1'b1;b=1'b0;c_in=1'b0;
        #100	a=1'b1;b=1'b0;c_in=1'b1;
        #100	a=1'b1;b=1'b1;c_in=1'b0;
        #100	a=1'b1;b=1'b1;c_in=1'b1;
    end 
endmodule


---
## Question 2
**Verilog Code - 4 Bit Ripple Carry Adder**

module nbitadder(a,b,s,c_out);
    parameter n=4;
    input [n-1:0] a;
    input [n-1:0]b;
    output [n-1:0] s;
    output c_out;
    wire [n-1:0] c;
    genvar i;
    generate
        for (i = 0; i<n; i=i+1) 
        begin
            if (i==0) begin
                halfadder h(a[0],b[0],s[0],c[0]);
            end
            else begin
                fulladder f(a[i],b[i],c[i-1],s[i],c[i]);
            end
        end
    assign c_out = c[n-1];
    endgenerate
endmodule

**Verilog Code - TestBench**

module nbitadder_bench();
    parameter n=4;
    reg [n-1:0] a,b;
    wire [n-1:0] s;
    wire c_out;
    nbitadder g(a,b,s,c_out);
    initial
    begin
        $monitor("a=%b,b=%b,s=%b,c_out=%b",a,b,s,c_out);
                a[3]=1'b0;a[2]=1'b1;a[1]=1'b1;a[0]=1'b0;
                b[3]=1'b0;b[2]=1'b0;b[1]=1'b1;b[0]=1'b0;
        #100    a[3]=1'b1;a[2]=1'b1;a[1]=1'b1;a[0]=1'b1;
                b[3]=1'b0;b[2]=1'b0;b[1]=1'b0;b[0]=1'b1;
    end 
endmodule


---

## Question 3
**Verilog Code - 2:1 Multiplexer using Structural Modelling**

module multiplexer(i1,i2,s,y);
    input i1,i2,s;
    output y;
    wire w1,w2,w3;
    not(w1,s);
    and(w2,i1,w1);
    and(w3,i2,s);
    or(y,w2,w3);
endmodule

**Verilog Code - TestBench**

module mux_bench();
    reg i1,i2,s;
    wire y;
    multiplexer m(i1,i2,s,y);
    initial
    begin
        $monitor("i1=%b,i2=%b,s=%b,y=%b",i1,i2,s,y);
                i1=1'b0;i2=1'b0;s=1'b0;
        #100	i1=1'b0;i2=1'b0;s=1'b1;
        #100	i1=1'b0;i2=1'b1;s=1'b0;
        #100	i1=1'b0;i2=1'b1;s=1'b1;
        #100	i1=1'b1;i2=1'b0;s=1'b0;
        #100	i1=1'b1;i2=1'b0;s=1'b1;
        #100	i1=1'b1;i2=1'b1;s=1'b0;
        #100	i1=1'b1;i2=1'b1;s=1'b1;
    end
endmodule


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