# Lab 09 Name: CHATSE SIDDHANT MADHUKAR Roll No.: CS22B016 --- ## Question 1 **Verilog Code** ```verilog= module ALU #(parameter n=4)(a,b,controller,result); input [n-1:0]a,b; input [1:0]controller; output [n-1:0]result; wire [n-1:0]addition_result,subtraction_result,and_result,or_result; assign addition_result = a+b; assign subtraction_result = a-b; assign and_result = a&b; assign or_result = a|b; assign result = (controller==2'b00) ? addition_result : (controller==2'b01) ? subtraction_result : (controller==2'b10) ? and_result : (controller==2'b11) ? or_result : 0; endmodule module ALU_test; reg [3:0]a,b; reg [1:0]controller; wire [3:0]result; ALU uut(.a(a),.b(b),.controller(controller),.result(result)); initial begin a=4'b0000; b=4'b0000; controller=2'b00; end always #2 a=a+1'b1; always #1 b=b+1'b1; always #16 controller=controller+1'b1; initial #100 $finish; endmodule ``` Output is as shown: 1. ![11](https://hackmd.io/_uploads/ryVn4h-eR.png) 2. ![12](https://hackmd.io/_uploads/H1JTE3-lR.png) 3. ![13](https://hackmd.io/_uploads/SJqpEhWeR.png) --- ## Question 2 **Verilog Code** ```verilog= module simple_processor(input [7:0]instruction); reg [7:0] memory [255:0]; reg [7:0] reg_file [15:0]; reg opcode; reg [1:0] reg_dest; reg [1:0] reg_source; reg [2:0] offset; reg [7:0] data_out; reg [7:0] address; always @(*) begin opcode = instruction[7]; reg_dest = instruction[6:5]; offset = instruction[4:2]; reg_source = instruction[1:0]; end always @(*) begin case(opcode) 1'b0: begin memory[address] = reg_file[reg_source]+offset; data_out = memory[address]; reg_file[reg_dest] = data_out; end 1'b1: begin address = reg_file[reg_source]+offset; memory[address] = reg_file[reg_dest]; data_out = 8'b00000000; end default: begin data_out = 8'b00000000; end endcase end endmodule ``` --- ## Question 3 ```cpp= #include<stdio.h> int fact(int n) { if(n==0) { return 1; } return n * fact(n-1); } int main() { int a=5; printf("%d\n",fact(5)); return 0; } ``` The number of instructions are counted in this program using inscount0 tool. Commands executed are as follows: ```cpp= ../../../pin -t obj-intel64/inscount0.so -o inscount0.log -- /home/system/Desktop/Computer_Organisation_Lab/Lab9/first.out cat inscount0.log ``` Output is as follows: ``` Count 125605 ``` ---