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title: PQC Research Papers; Software Optimization & Hardware Implementation

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#  PQC Research Papers; Software Optimization & Hardware Implementation

## 1. Efficient Hardware Implementation of Constant Time Sampling for HQC
**Authors:** Maximilian Schoeffel, Johannes Feldmann, Norbert Wehn  
https://arxiv.org/pdf/2309.16493v3

> Target Platform:FPGA: Xilinx Artix-7 (xc7a100tftg256-1), Vivado 2020.1Measured latency in cycles and µs, LUT/FF/BRAM usage.
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## 2. Evaluating Post-Quantum Cryptographic Algorithms on Resource-Constrained Devices
**Authors:** Jesus Lopez†, Viviana Cadena†, Mohammad Saidur Rahman  
https://arxiv.org/pdf/2507.08312v1

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## 3. Complexity of Post-Quantum Cryptography in Embedded Systems and Its Optimization Strategies
**Authors:** Omar Alnaseri∗, Yassine Himeur¶, Shadi Atalla¶, Wathiq Mansoor¶  
https://arxiv.org/pdf/2504.13537v1

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## 4. A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium

**Authors:** Cankun Zhao1,+, Neng Zhang1,+, Hanning Wang1, Bohan Yang1, Wenping Zhu1, Zhengdong Li1, Min Zhu2, Shouyi Yin1, Shaojun Wei1, Leibo Liu1  
https://tches.iacr.org/index.php/TCHES/article/view/9297/8863
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## 5. RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography
**Authors:** Tim Fritzmann1, Georg Sigl1, Johanna Sepúlveda2  
https://eprint.iacr.org/2020/446.pdf
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## 6. Speeding up R-LWE Post-Quantum Key Exchange
**Authors:** Shay Gueron1,2, Fabian Schlieker3  
https://eprint.iacr.org/2016/467.pdf
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## 7. Post-Quantum Cryptography for Internet of Things: A Survey on Performance and Optimization
**Authors:** Tao Liu, Gowri Ramachandran, Raja Jurdak
https://arxiv.org/pdf/2401.17538

## 8.High-Performance Hardware Implementation of  Crystals-Dilithium Based on Improved MDC-NTT

Using Xilinx Artix-7 platform
https://ieeexplore.ieee.org/document/11024171/

## 9.Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium

Using one of the smallest Zynq FPGA, Zynq Ultrascale+
https://eprint.iacr.org/2022/496

## 10.Serialized lightweight SHA-3 FPGA implementations
Using Virtex-5 and Virtex-6 FPGAs
https://linkinghub.elsevier.com/retrieve/pii/S0141933117302818

## 11.Beyond the Limits: SHA-3 in Just 49 Slices
Using Virtex-5 (V-5) or Virtex-6 (V-6), xc5vlx50t and xc6vlx75t, also on V7 for future comparison
https://ieeexplore.ieee.org/document/8892262

## 12.Proteus: A Pipelined NTT Architecture Generator
Using Xilinx Virtex-7 XCVX485T FPGA
https://eprint.iacr.org/2023/267

## 13.Low-cost and area-efficient FPGA implementations of lattice-based cryptography
Using smallest Xilinx Spartan-6 FPGA.
https://ieeexplore.ieee.org/document/6581570/