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# System prepended metadata

title: SOCStudy

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# SOC design Study Journel

I will try my best on this course !! 


## Lab0: collaborative-learning-checklist
- Download the Slack application, and join soclab channel in Slack
- Subscribe Github/bol-edu/HLS-SOC-Discussion
- Create Personal Github
- Create Hackmd.io account, and create first document: SOCStudy.md

## Lab1: Design Flow from HLS to output bitstream to FPGA board
- Install Work Environment
    -  Install Oracle VM VirtualBox 6.1.42 and Extension pack
    - Install Xilinx suite tool(vitis、vitis_hls、vivado).
- Use Xilinx tool vitis_hls to generate IP
- Use Xilinx tool Vivado to generate bitstream
- Verify design work correctly on FPGA board
## Lab2: Design FIR with AXI interface using HLS
- Use HLS to design FIR
- Use Xilinx tool vitis_hls to generate IP
- Use Vivado generate AXI-Master interface or  AXI-Stream interface with ZYNQ
- Use Xilinx tool Vivado to generate bitstream
- Verify design work correctly on FPGA board
## Lab3: Design FIR with AXI interface using Verilog
- Use Verilog to design FIR
- Test FIR functionality using Verilog 
- Design AXI-lite and AXI-Stream interfaces using Verilog
- Design Block-level Protocol using Verilog
## Lab4-1: Execute Code in User Memory
- Design Bram in user_project
  - Design the controller connected with wishbone bus 
- Write FIR using C language
## Lab4-2: FIR software/hardware co-design
- Using Firmware to move data in/out FIR
  - Design MMIO configuration address space 
  - Use exmem-FIR for code storage/access
  - RISC-V moves X(input)/Y(output) FIR engine
- Integrate Hardware (FIR & exmem-FIR) into Caravel user project area (add WB interface)
  - Design WB decoder & WB-AXI interface
- Record latency for firmware to feed data 
## Lab5: Caravel FPGA - build from each IP
- Build the three IP: caravel_ps, read_romcode, output_pin
- Build the FPGA bitstream – integrate the Caravel soc and the three IPs
- Validate it on FPGA with the Jupyter Notebook run on PS
## Lab6: Workload optimized SOC – baseline
- Simulation on Matrix Multiplication, Quick Sort, FIR and UART separately
- Firmware code integrates Matrix Multiplication, Quick Sort, FIR and UART
- Hardware integrates exmem-fir with UART design in user project area
- Modify testbench to include the test for Matrix Multiplication, Quick Sort, FIR and UART
- Verify if the firmware code can execute on FPGA

