---
# System prepended metadata

title: VLSI Design Midterm 考古題
tags: [' VLSI', 111-1]

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---
title:  VLSI Design Midterm 考古題
tags: 111-1, VLSI
---
[TOC]
# VLSI Design Midterm 考古題


## 1. Explain the following terms or answer the following short questions:
### A. Feature size



### B. Mask



### C. Design rule


### D. Well contact


### E. Draw the waveform of the nonoverlapping clock



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## 2. Short questions
### A. What is the fanout of a gate?



### B. What are design rules used for in chip design?


### C. What is setup time? what is hold time?


### D. Draw the waveform of two-phase nonoverlapping clock.


### E. What is the purpose of transistor sizing?
- 因為nmos,pmos速度不同,而pmos較慢,所以需調整transistor sizing使其速度達到一致


### F. What is clock skew? What problems may it cause in VLSI circuits?
#### 例如,兩flip-flop串連![](https://i.imgur.com/0jmnQaL.png) clk2較慢到達,將會造成clock skew,會使資料有誤

### H. Draw the waveform of two-phase nonoverlapping clock.
#### ![](https://i.imgur.com/5K4H6cY.png)

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## 3. Explain what are static CMOS and pseudo NMOS, respectively, with the circuits for an inverter. 
### Explain how they work.
#### ![](https://i.imgur.com/Dfp0sbq.png)

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## 4. The following figure is an inverter on the wafer:
### A. What is the purpose of SiO2? What is the purpose of metal1?
#### SiO2 當絕緣體，使Y部分的電荷能在基底產生反極性的電荷
#### Metal1 輸入，輸出用的金屬導線
### B. If the well tap and substrate tap are added, where should we put them in the figure?
#### ![](https://i.imgur.com/m4ulrZl.png)

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## 5. Three-input NAND gate:
### A. Draw the diagram of a three-input NAND gate by using CMOS transistors
#### ![](https://i.imgur.com/60WeM0E.png)
### B. Explain why the gate exhibits NAND behavior
#### ![](https://i.imgur.com/Tws3rug.png)
#### A,B,C都為1時Y short to GND→Y=0
#### A,B,C其中任一個為0時Y short to VDD → Y=1
### C. If the size of all transistors is the same(length and width), which of(0→1)and(1→0) is faster? Why?
#### 1→0 較慢  0→1 叫快，因為nMOS 串連3個，會比原本慢3倍，而pMOS本身慢2倍，而3>2

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## 6. Testing: In the following diagram, give all the test vectors that can tell site i has a stuck-at-1 fault? Give your reasoning
#### ![](https://i.imgur.com/zabwPdb.png)

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## 7. Cascading precharged gates has the false discharge problem. However, using domino logic solves the problem. Why? Give an example circuit and explain it.
#### ![](https://i.imgur.com/8tqjEvC.png) precharged 階段x1,x2被設為 1→x1‾,x2‾為0
#### 將x1‾,x2‾設為0為使電路運作正確的必要條件，因為x1‾,x2‾可以由00, 0→1, 1→1, 但不能1→0, 1→0會因為一開始就把中荷漏掉而錯誤，doming logic裡的inverter（逆變器）就是為了確保x1,x2在precharge（緩啟器）為1時x1‾,x2‾被設為0,避免漏電

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## 8. Inverter:
### A. Draw the diagram of an inverter by using CMOS transistors.
#### ![](https://i.imgur.com/DmK2neF.png)
### B. Explain why it exhibits the inverter behavior.
#### ![](https://i.imgur.com/2GopJlt.png)
### C. If the size of all transistors is the same(length and width), which of (0→1) and (1→0) is faster? Why?
#### 1→0 is faster, 因為電子移動的速度較快
### D. Draw the layout of the inverter by giving the stick diagram.
#### ![](https://i.imgur.com/N95ocbc.png)

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## 9. Boolean function:
### A. Draw the diagram of the two-input NAND gate by using CMOS transistors.
#### ![](https://i.imgur.com/8wwhM8p.png)
### B. Draw the layout of the circuit by giving the stick diagram.
#### ![](https://i.imgur.com/miYEG6y.png)
### C. Give the width ratio of each transistor, such that the switching speed of(0→1) and(1→0) is about the same. Assume the minimum ratio of the sized transistor is 3/2.
#### 2/3 * 2 * 3/2 = 4/2  
#### nmos電晶體(1→0) 2/3 
#### pmos電晶體(0→1) 2/4
### D. Draw the diagram of the two-input NAND gate by using CMOS transistors. Give the width ratio of each transistor, such that the switching speed of(0→1) and (1→0) is about the same.
#### ![](https://i.imgur.com/czRcNgU.png)
### E. Draw the diagram of the Boolean function Z=~[A(B+C)] by using CMOS transistors
#### ![](https://i.imgur.com/lEFTNeO.png)

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## 10. Adder:
### A. Give the truth table for a 1 -bit full adder(three inputs and two outputs).
#### ![](https://i.imgur.com/MgmH3OL.png)
### B. Draw the logic diagram of the above 1 -bit full adder.
#### ![](https://i.imgur.com/PPzxOV9.png)

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## 11. Multiplexer:
### A. Draw the circuit diagram of a 2:1 multiplexer using only NAND gates and only transmission gates, respectively.
#### ![](https://i.imgur.com/NmxeK8b.png)
### B. Draw the circuit diagram of a 2:1 multiplexer using only transmission gates.
#### ![](https://i.imgur.com/QCe8nYi.png)
### C. Discuss the advantages and disadvantages of the above two approaches, respectively.
#### ![](https://i.imgur.com/CBjgiwF.png)

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## 12. What is setup time? What is hold time? Give an example for each to explain them
#### Setup time: Data訊號要在clock edge之前要保持穩定的最短時間
#### Hold time: Data訊號要在clock edge之後要保持穩定的最短時間

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## 13. What in Moore's Law?
#### 26個月電晶體數增加1倍效能也提升1倍。
### What is it's impact on VLSI? 
#### 速度將更快成本更低。
### What problems may we encounter in future VLSI chip design as the technology keeps improving? Give your opinions.
#### 變很小製作難度提高也更難調整。

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## 14.
![](https://i.imgur.com/VpKh47R.png)
### What logic function is the following gate? 
#### NAND(3 input) gate 
### Point out where the well or substrate contacts are.
#### ![](https://i.imgur.com/7FU1Ot0.png)

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## 15. D-latch and flip-flop:
![](https://i.imgur.com/XVCMb9Q.png)
### A.Draw the waveform of the Q signal based on the following CLK and D for a D latch.
### B.Draw the waveform of the Q signail if D is for D flip-flop.
#### ![](https://i.imgur.com/wmuDA9S.png)

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:::warning
Verilog 期中不考
:::

## 16. Verilog
### A. Give any two statements which can be synthesized. Give any two statements which cannot be synthesized.
#### can: always@..., a=b+c
#### can't: #10, inital
### B. What is the difference between the two statements: #10a=b+c and a=#10b+c?
#### #10 a=b+c: delay 10 time unit then do a=b+c
#### a=#10 b+c: b+c delay 10 time unit then set value to a
### C. What is the difference between blocking statements and non-blocking statements? Give an example for each.
#### blocking statements 是執行的時候不會照著順序,會亂跳 ![](https://i.imgur.com/sCoY4Fb.png)
#### non-blocking statements 會等新值更新舊值後,一個一個照順序跑 ![](https://i.imgur.com/SKkgRF4.png)
### D. What does statement "always @(sel or b or c)" mean?
#### 若 sel or b or c 其中一個改變則做always裡的語句
### E.We mention in our class that the following Verilog statements are not correct for designing a shift register. Why? What should be the correct design?
    always @(posedge clk)d2=d1;
    always @(posedge clk)d3=d2;
    always @(posedge clk)d4=d3;
#### always @(posedge clk)d2<=d1;<br>always @(posedge clk)d3<=d2;<br>always @(posedge clk)d4<=d3;
### F. What does the statement with assign mean?Give an example
#### 持續指定永遠處於活動狀態。assign sum=a+b+carryin;
#### 持續指定sum當其a、b、carryin發生變化時sum的值也會相對的改變
### G. Give the input/output table for a two-input NAND gate if the input value can be 0,1,x, and z.
#### ![](https://i.imgur.com/pZB6eK8.png)
### H. What does the delay #(2:3:4, 4:5:6, 7:8:9)
#### 2:3:4 - 延遲的Min, 4:5:6 - 延遲的上升或下降, 7:8:9 - 延遲的Max .





2014(108 points 1-B 5-A 5-C )
2014(110 points 3-C)
2011(110 points 6,8)
