---
# System prepended metadata

title: VLSI verilogHW
tags: [' VLSI', 111-1]

---

---
title:  VLSI verilogHW
tags: 111-1, VLSI
---
[TOC]
# VLSI verilogHW

## HW1-1
### Q1.	
![](https://i.imgur.com/FT68W0j.png)
- Design an 4-bit adder with Verilog in structural model. The adder is composed by four one-bit carry-ripple adder. Your design module should be verified by the test module. Submit your file (combining the design module and the test module) to the e-learning by the deadline.


![](https://i.imgur.com/RsAZoqk.png)
```verilog!
//flad.v
module flad(a, b, cin, s, cout);
	input a, b, cin;
	output s, cout;
	assign s = (a^b) ^cin;
	assign cout = (a&cin) | (b&cin) | (a&b);
endmodule
```
```verilog!
//crad.v
module crad( A0, A1, A2, A3, B0, B1, B2, B3, S0, S1, S2, S3, C3);
	input A0, A1, A2, A3;
	input B0, B1, B2, B3;
	output S0, S1, S2, S3, C3;
	wire C0, C1, C2;

flad FA_A(.a(A0), .b(B0), .cin(0), .s(S0), .cout(C0) );
flad FA_B(.a(A1), .b(B1), .cin(C0), .s(S1), .cout(C1) );
flad FA_C(.a(A2), .b(B2), .cin(C1), .s(S2), .cout(C2) );
flad FA_D(.a(A3), .b(B3), .cin(C2), .s(S3), .cout(C3) );

endmodule
```
```verilog!
// crad.vt
`timescale 1ns/1ns
module test;
reg a0, a1, a2, a3, b0, b1, b2, b3;
wire c, s0, s1, s2, s3;

crad U0 ( .A0(a0), .A1(a1), .A2(a2), .A3(a3), .B0(b0), .B1(b1), .B2(b2), .B3(b3), .S0(s0), .S1(s1), .S2(s2), .S3(s3), .C3(c) );

initial begin
a0=0;
a1=0;
a2=0;
a3=0;
b0=0;
b1=0;
b2=0;
b3=0;

#5;
a0=1;
a1=0;
a2=1;
a3=0;
b0=0;
b1=1;
b2=0;
b3=1;

#5;
a0=1;
a1=0;
a2=1;
a3=0;
b0=1;
b1=0;
b2=1;
b3=0;

#5;
a0=1;
a1=1;
a2=1;
a3=1;
b0=1;
b1=1;
b2=1;
b3=1;
end

initial begin
$fsdbDumpfile("crad.fsdb");
$fsdbDumpvars(0, test);
end

endmodule
```

6s: (A3A2A1A0=0101) + (B3B2B1B0=1010) =>(CS3S2S1S0=01111)
![](https://i.imgur.com/0hFldgH.png)
11s: (A3A2A1A0=0101) + (B3B2B1B0=0101) =>(CS3S2S1S0=01010)
![](https://i.imgur.com/aPzjYP2.png)
16s: (A3A2A1A0=) + (B3B2B1B0=) =>(CS3S2S1S0=11110)
![](https://i.imgur.com/PwUaCXJ.png)


# HW1-2
## Q2
![](https://i.imgur.com/AMsgDtM.png)
## Answer
### Code
```verilog=
// flipflop.v
module flipflop(q, clk, rst, d);
	input clk, rst, d;
	output q;
	reg q;

	always @(posedge clk or posedge rst)
		begin
		if (rst)
			q <= 1;
		else
			q <= d;
		end

endmodule
```

```verilog=
// prsg.v
module prsg(Q0, Q1, Q2, Clk, Rst);
	input Clk, Rst;
	output Q0, Q1, Q2;
	wire XORq0q2;
	wire Q0, Q1, Q2;

	xor xor1(XORq0q2, Q0, Q2);

	flipflop F0( .q(Q0), .clk(Clk), .rst(Rst), .d(XORq0q2));
	flipflop F1( .q(Q1), .clk(Clk), .rst(Rst), .d(Q0));
	flipflop F2( .q(Q2), .clk(Clk), .rst(Rst), .d(Q1));

endmodule
```

```verilog=
// prsg.vt
`timescale 1ns/1ns
module test();

reg clk, rst;
wire q0, q1, q2;

prsg prsg0(.Q0(q0),
 .Q1(q1),
 .Q2(q2),
 .Clk(clk),
 .Rst(rst)
);

initial begin
clk=0;
rst=1;
#1 rst=0;

#80 $finish;

end

always #5 clk=~clk;


initial begin
$fsdbDumpfile("prsg.fsdb");
$fsdbDumpvars(0, test);
end

endmodule

```

### Wave
- Q0Q1Q2 = 111→011→101→010→001→100→110→111→...
- ![](https://i.imgur.com/LnmvlG5.png)










