---
title: 系統晶片 -verilog
tags: 系統晶片
---
[TOC]

---

# 系統晶片 verilog

## 從「軟體設計領域」跨入「硬體設計領域」
### Concurrent v.s. Sequential

### Blocking v.s. Nonblocking
- **同一個always block裡**，只能選**一種**給值的方式，意思就是 blocking 跟 nonblocking 只能選一種用，**不能混用**
- example:
- 
- **組合邏輯電路** v.s. **循序邏輯電路**

- 化複雜為簡單
- **乘法**: 乘2的幂次方就可以用位移代替：a <= b * 4;可以寫成a <= b << 2。
- **除法**: 除法也是，取餘數的話像是a <= b % 16; 可以寫成 a <= b[3:0]這樣。

#### Blocking
- 組合邏輯電路(Combinational Circuits)
1. 
2. 

- 循序邏輯電路(Sequential Circuit)
1. 

#### Nonblocking
- 循序邏輯電路(Sequential Circuit)

### Delayed evaluations v.s. Delayed assignments

always@(＊)，意思就是當裡面有任何訊號線改變是就會執行always block的行為．

## 乘法器
- 4-bit

module multiplier(a,b, ab);
input [3:0] a,b;
output [7:0] ab;

wire [3:0] t0,t1,t2,t3;

assign t0 = (b[0]==1) ? a : 4'h0;
assign t1 = (b[1]==1) ? a : 4'h0;
assign t2 = (b[2]==1) ? a : 4'h0;
assign t3 = (b[3]==1) ? a : 4'h0;

assign ab=t0+(t1<<1)+(t2<<2)+(t3<<3);

endmodule

- 32 bits
1. 
2. multiplication.v

//multipli
module multiplication(
input [31:0] a,b,
output [63:0] ab
);

wire [31:0] t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30,t31;

assign t0 = (b[0]==1) ? a : 4'h0;
assign t1 = (b[1]==1) ? a : 4'h0;
assign t2 = (b[2]==1) ? a : 4'h0;
assign t3 = (b[3]==1) ? a : 4'h0;
assign t4 = (b[4]==1) ? a : 4'h0;
assign t5 = (b[5]==1) ? a : 4'h0;
assign t6 = (b[6]==1) ? a : 4'h0;
assign t7 = (b[7]==1) ? a : 4'h0;
assign t8 = (b[8]==1) ? a : 4'h0;
assign t9 = (b[9]==1) ? a : 4'h0;
assign t10 = (b[10]==1) ? a : 4'h0;
assign t11 = (b[11]==1) ? a : 4'h0;
assign t12 = (b[12]==1) ? a : 4'h0;
assign t13 = (b[13]==1) ? a : 4'h0;
assign t14 = (b[14]==1) ? a : 4'h0;
assign t15 = (b[15]==1) ? a : 4'h0;
assign t16 = (b[16]==1) ? a : 4'h0;
assign t17 = (b[17]==1) ? a : 4'h0;
assign t18 = (b[18]==1) ? a : 4'h0;
assign t19 = (b[19]==1) ? a : 4'h0;
assign t20 = (b[20]==1) ? a : 4'h0;
assign t21 = (b[21]==1) ? a : 4'h0;
assign t22 = (b[22]==1) ? a : 4'h0;
assign t23 = (b[23]==1) ? a : 4'h0;
assign t24 = (b[24]==1) ? a : 4'h0;
assign t25 = (b[25]==1) ? a : 4'h0;
assign t26 = (b[26]==1) ? a : 4'h0;
assign t27 = (b[27]==1) ? a : 4'h0;
assign t28 = (b[28]==1) ? a : 4'h0;
assign t29 = (b[29]==1) ? a : 4'h0;
assign t30 = (b[30]==1) ? a : 4'h0;
assign t31 = (b[31]==1) ? a : 4'h0;

assign ab=t0+(t1<<1)+(t2<<2)+(t3<<3)+(t4<<4)+(t5<<5)+(t6<<6)+(t7<<7)+(t8<<8)+(t9<<9)+(t10<<10)+(t11<<11)+(t12<<12)+(t13<<13)+(t14<<14)+(t15<<15)+(t16<<16)+(t17<<17)+(t18<<18)+(t19<<19)+(t20<<20)+(t21<<21)+(t22<<22)+(t23<<23)+(t24<<24)+(t25<<25)+(t26<<26)+(t27<<27)+(t28<<28)+(t29<<29)+(t30<<30)+(t31<<31);

endmodule

3. error message
4.