---
# System prepended metadata

title: Chapter 3-Gate-Level Minimization
tags: [Digital IC Design]

---

---
tags: Introduction to Digital System
---
# Chapter 3-Gate-Level Minimization
## The Map Method
1. Rules:
    1. Draw a square and split them into several small squares.
    2. Fill in minterms in each small squares.
    3. Write the corresponding binary number aside the margins. Note that the binary number is from 0 and the next binary number should be only changed a bit of number.
    4. Fill in the outcomes in small squares.
    5. Sum the products which is 1 together. If there is a products aside, we can simplify them.
        * ※Sums like below can also be merged first
            ![](https://i.imgur.com/i4yD48l.png)
        * ※Terms with the least adjacent terms should be considered first.
        * ※A box that 8->4->2->1 terms are adjacent should be considered in order.
    6. Don't-Care Conditions: A don't-care minterm is a combination of variables whose logical value is not specified. In a k-map, it is marked "X", which can be 0 or 1.
2. Examples:
    1. Two-Variable K-Map
        ![](https://i.imgur.com/ukIH7UK.png)
        ![](https://i.imgur.com/gL5CieD.png)
        ![](https://i.imgur.com/mnPNHhv.png)
    2. Three-Variable K-Map:
        ![](https://i.imgur.com/QCQ1eTD.png)
        ![](https://i.imgur.com/NUcoblB.png)![](https://i.imgur.com/x8b1W9t.png)
        ![](https://i.imgur.com/jVuyzH7.png)
    3. Four-Variable K-Map:
        ![](https://i.imgur.com/vX2ORlZ.png)
## NAND and NOR Implementation
1. NAND Implementation
    1. Introduction: AND, OR, NOT gates can be replaced by NAND gates.
        ![](https://i.imgur.com/mcV389Y.png)
    2. Implementation:
        ![](https://i.imgur.com/0ww8nGY.png)
        1. Two Level Implementation
            ![](https://i.imgur.com/AgSlU94.png)
        2. Multilevel NAND Circuits
            1. Draw the SOP
            2. Convert all AND gates to NAND gates with AND-invert graphic symbols.
            3. Convert all OR gates to NAND gates with invert-OR graphic sympls.
            4. Check all the bubbles in the diagram. For every bubble that is not compensated by another small circle along the same line, insert an inverter or complement the input literal.
2. NOR Implementation
    1. Introduction
        ![](https://i.imgur.com/j4FNHmY.png)
    2. Implementation
        ![](https://i.imgur.com/GGloFQd.png)
        1. Draw the POS
        2. Convert
3. Implementation of XOR
    1. Definition
        1. Two Variables
            1. $x\bigoplus y=x'y+xy'$
            2. $(x\bigoplus y)'=xy+x'y'$
            ![](https://i.imgur.com/QqTL71Q.png)
        2. N Variables
            ![](https://i.imgur.com/BIHwJJW.png)
            ![](https://i.imgur.com/SsEDQqp.png)
    2. Properties
        1. $x\bigoplus0=x$
        2. $x\bigoplus1=x'$
        3. $x\bigoplus x=0$
        4. $x\bigoplus x'=1$
        5. $x\bigoplus y'=x'\bigoplus y=(x\bigoplus y)'$
        6. $x\bigoplus y=y\bigoplus x$
        7. $(x\bigoplus y)\bigoplus z=x\bigoplus(y\bigoplus z)$
    3. Parity Generation and Checking
        Take even parity for example:
        $Parity\ Bit\ P=x\bigoplus y\bigoplus z...\\Parity\ Error\ Check\ C=x\bigoplus y\bigoplus z...\bigoplus P$

**Reference**
NCKUCSIE 1101_Introduction to Digital System
Digital Design With an Introduction to The Verilog HDL, VHDL and System Verilog 6/e by M.Morris Mano Michael D. Ciletti