---
# System prepended metadata

title: Chapter 5-MOS Field-Effect Transistors (MOSFETs)
tags: [Microelectronic Circuits]

---

---
tags: Microelectronic Circuits
---
# Chapter 5-MOS Field-Effect Transistors (MOSFETs)
## Device Structure
![](https://i.imgur.com/YXxxfak.png)
![](https://i.imgur.com/tWC6oET.png)
1. The transistor is built on a p-type substrate, a single-crystal silicon wafer that provides physical support for the device.
2. Two heavily doped n-type regions,indecated as the $n^+$ source and the $n^+$ drain regions, are created in the substrate.
3. A thin layer of $SiO_2$ of thickness $t_{ox}$, which is an extrical insulator, is grown on the surface of the substrate, covering the area between the source and drain regions.
4. Metal is deposited on top of that oxide layer to form what's called the gate electrode of the device. Matal contacts are also made to the source regin, the drain region, and the substrate, also known as the body. This creates four terminals: the gate terminal (G), three source terminal (S), the drain terminal (D), and the substrate or body terminal (B).
## Operations
### NMOS
1. Introductions
    1. The positive voltage on the gate causes the free holes to be repelled from the area of the substrate. These ones are pushed downward into the substrte leaving behind a carrier-depletion region.
    2. As well, the positive gate voltage attrcts electrons from the $n^+$ source and drain regions into the channel region. When a sufficient number of electrons accumulate near the surface of the substrate under the gate, an n region is in effect created, connecting the source and drain regions to one another. Now if we apply a voltage between drain and source, current flows through this inducedn region, carried by the mobile electrons.
    3. The value $v_{GS}$ at which a sufficient number of mobile electrons accumulate under the gate to form a conducting channel is called the threshold voltage, $V_t$ and $V_t$ is positive.
    4. The current flows through the channel when $v_{DS}$ is applied.
2. Operations
    1. Zero $v_{DS}$
        1. The  voltage across this parallel-plate capacitor, that is, the voltage across the oxide, must exceed $V_t$ for a channel to form.
        2. When $v_{DS}=0$, the voltage evergy point along the channel is zero, and the voltage across the oxide is uniform and equal to $v_{GS}$. The excess of $v_{GS}$ over $V_t$ is called the effective voltage or the overdrive voltage. We denote 
            $v_{OV}=v_{GS}-V_t$
        3. We can express the magnitude of the electron charge in the channel by
            $\begin{cases}|Q|=C_{ox}(WL)v_{OV}\\C_{ox}=\frac{\epsilon_{ox}}{t_{ox}}\end{cases},\ where C_{ox},\ called\ the\ oxide\ capacitance,\ is\ the\\capacitance\ of\ the\ parallel-plate\ capacitor\ per\ unit\ gate\ area,\ W\ is\ the\ width\\of\ the\ channel,\ L\ is\ the\ length\ of\ the\ channel,\ \epsilon_{ox}\ is\ the\ permittivity\ of\ the\\silicon\ dioxide\ \epsilon_{ox}=3.9\epsilon_0=3.45\times10^{-11}[F/m],\ and\ t_{ox}\ is \ the\ oxide thickness$.
			And the totla capacitance is
			$C=C_{ox}WL$
	2. Applying a Small $v_{DS}$
		* A current $i_D$ flows through the induced n channel. Current is carried by free electrons traveling from sourse to drain. Because $v_{DS}$ is small we can continue to assume that the voltage between that gate and various points along the channel remains approximately constant and equal to the value at the source end, $v_{GS}$. Thus, the effective voltage between the gate and the various points along the channel remains equal to $v_{OV}$.
			$\begin{cases}\frac{|Q|}{L}=C_{ox}Wv_{OV}\\|E|=\frac{v_{DS}}{L}\\Electron\ drift\ velocity=\mu_n|E|=\mu_n\frac{v_{DS}}{L}\end{cases}\\\Rightarrow i_D=[(\mu_nC_{ox})(\frac{W}{L})v_{OV}]v_{DS}$
			For small $v_{DS}$, te channel bhavves as a linear resisance whose value is controlled by the overdrive voltage $v_{OV}$, which in turn is determined by $v_{GS}$ 
			$i_D=[(\mu_nC_{ox})(\frac{W}{L})(v_{GS}-V_t)]v_{DS}\\\Rightarrow The\ conductance\ g_{GS}=(\mu_nC_{ox})(\frac{W}{L})(v_{GS}-V_t)$
			1. The Process Transconductance
				$The\ Process\ conductance\ k'_n[A/V^2]=\mu_n[m^2/V\cdot s]C_{ox}[F/m^2]$
			2. The Aspect Ratio
				$The\ aspect\ ratio=\frac{W}{L}$ and the MOSFET transconductance parameter $k_n[A/V^2]=k'_n(\frac{W}{L})$
			3. The Overdrive Voltage
				![](https://i.imgur.com/XA2cmju.png)
                With $v_{DS}$ kept small, the MOSFET behaves as a linear resistance $r_{DS}$ whose value is controlled by the gate voltage $v_{GS}$
                $\begin{split}r_{DS}&=\frac{1}{g_{DS}}\\&=\frac{1}{(\mu_nC_{ox}(W/L)v_{OV})}\\&=\frac{1}{(\mu_nC_{ox}(W/L)(v_{GS}-V_t))}\end{split}$
                The resistance is infinite for $v_{GS}\leq V_t$ and decreases as $v_{GS}$ is increased above $V_t$.
	3. Operation as $v_{DS}$ Is Increased
	    ![](https://i.imgur.com/6NJYwvx.png)
        $v_{DS}$ increases form zero to $v_{DS}$. Thus the voltage the gate and points along the channel decreases form $v_{GS}=V_t+v_{OV}$ at the source end to $v_{GD}=v_{GS}-v_{DS}=V_t+v_{OV}-v_{DS}$ at the drain end.
        ![](https://i.imgur.com/d1BWpUz.png)
        As $v_{DS}$ increased, the channel becomes more tapered and its resistabce ubcreases correspondingly. Thus the $i_D-v_{DS}$ curve bends.
        ![](https://i.imgur.com/Y0ONJOr.png)
        The charge in the tapered channel is propotional to the channel cross-secontial area. This area in turn can ve seen as propotional to $\frac{1}{2}[v_{OV}+(v_{OV}-v_{DS})]=(v_{OV}-\frac{1}{2}v_{DS})$. Thus, the relationaship between $i_D$ and $v_{DS}$ can be found by replacing $v_{OV}$
        $\begin{split}i_D&=k'_n(\frac{W}{L})(v_{OV}-\frac{1}{2}v_{DS})v_{DS}\\&=k'_n(\frac{W}{L})[(v_{GS}-V_t)v_{DS}-\frac{1}{2}v_{DS}^2]\end{split}$
        Above we assumed that even though the channel became tapered, it still had a finite depth at the drain end. This is achieved by keeping $v_{DS}$ sufficiently small that $v_{GD}$ exceeds $V_t$. Note that for this situation to occur, $v_{DS}$ must not exceed $v_{OV}$, for as $v_{DS}=v_{OV}$, $v_{GS}=V_t$, and the channel depth at the drain end reduces to zero.
    4. Operation for $v_{DS}\geq v_{OV}$: Channel Pinch-Off and Current Saturation
        ![](https://i.imgur.com/Y0ONJOr.png)
        ![](https://i.imgur.com/VcaecJP.png)
        When $v_{DS}$ reaches $v_{OV}$ and $v_{GD}$ correspondingly reaches $V_t$. The zero depth of the channel at the drain end gives rise to the term channel pinch-off. Increasing $v_{DS}$ beyond this value has no effect on the channel shape and charge, and the current through the channel remains constant at the value reached for $v_{DS}=v_{OV}$. We say that the drain current saturates at the value found by substituting $v_{DS}=v_{OV}$
        $\begin{split}i_{D}&=\frac{1}{2}k'_n(\frac{W}{L})v_{OV}^2\\&=\frac{1}{2}k'_n(\frac{W}{L})(v_{GS}-V_t)^2\end{split}$
        The MOSFET is then said to have entered the saturation region. The voltage $v_{DS}$ at which saturation occurs is denoted $v_{DSsat}$,
        $v_{DS}=v_{OV}=v_{GS}-V_t$
        * ※Channnel pinch-off does not mean channel blockage. Current continuous to flow throough the pinched-off channel, and the electrons that reach teh drain end of the channel are accelerated through the depletion regin that exists there and into the drain terminal. Any increase in $v_{DS}$ above $v_{DSsat}$ appears as a voltage drop across hte depletion region. Thus, both the current through the channel and the voltage drop across it remain constant in saturation.
### PMOS
![](https://i.imgur.com/KCznf3Q.png)
![](https://i.imgur.com/NWDSYX7.png)
1. To induce a channel a channel for current flow between source and drain, a negative vltage is applied to the gate. By increasing te maganitude of the negative $v_{GS}$ beyond the maganitude of the threshold voltage $V_{tp}$, wich by convention is negative, a p channel is established.
	$v_{GS}\leq V_{tp}$
2. To make a current $i_D$ flow in the p channel, we apply a negaive voltage $v_{DS}$ to the drain.
	$\begin{cases}k'_p=\mu_pC_{ox}\\k_p=k'_p\frac{W}{L}\end{cases}$
3. $v_{OV}=v_{SG}-|V_{tp}|$
#### Complementary MOS or CMOS
![](https://i.imgur.com/kkVqSKU.png)
## Circuit Symbol
* NMOS
    ![](https://i.imgur.com/9b1tQwD.png)
* PMOS
    ![](https://i.imgur.com/OvwN5Uu.png)
## Curreent-Voltage Characteristics
### NMOS
1. The $i_D-v_{DS}$ Characteristics
	![](https://i.imgur.com/PaBYm6j.png)
	![](https://i.imgur.com/6HV1Gwa.png)
	* Output Resistance
		![](https://i.imgur.com/G5C4dLR.png)
		![](https://i.imgur.com/lOyfiwY.png)
		1. $i_D$
			As $v_{DS}$ is increased, the channel pinch-off point moves slightly away from the drain, toword the source. In turn, the channel length is reduced, form $L$ to$L-\Delta L$ wich is known as chnnel-length modulation.
			$i_D=\frac{1}{2}k'_n\frac{W}{L}(v_{GS}-V_{tn})^2(1-\lambda[V^{-1}]v_{DS}),\ \lambda\ \text{is a device parameter}.$
		2. $V_A$
			$V_A=\frac{1}{\lambda}$
			Because $V_A$ is propotional to the channel length $L$.
			$V_A=V'_AL$
		3. $r_o$
			![](https://i.imgur.com/j5Kvztq.png)
			$r_o\equiv[\frac{\partial i_D}{\partial v_{DS}}]^{-1}_{v_{GS}\ constat}\\\Rightarrow r_o=[\lambda\frac{k'_n}{2}\frac{W}{L}(v_{GS}-V_n)^2]^{-1}\\Let\ i'_D=\frac{1}{2}k'_n\frac{W}{L}(v_{GS}-V_m)^2\\\Rightarrow r_o=\frac{1}{\lambda i'_D}=\frac{V_A}{i'_D}$
        * ※If $v_D=v_G$, operation is in the saturation mode.
2. The $i_D-v_{GS}$ Characteristic
    ![](https://i.imgur.com/A70SDJk.png)
    ![](https://i.imgur.com/Bz6ysUD.png)
    ![](https://i.imgur.com/TOdbXWc.png)
    $i_D=\frac{1}{2}k'_n(\frac{W}{L})v_{OV}^2$
### PMOS
![](https://i.imgur.com/SfCYMqv.png)
![](https://i.imgur.com/91QrqGj.png)
## Exercise
### P.320 Exercise 5.7
![](https://i.imgur.com/GLml65j.png)
![](https://i.imgur.com/gnLllRs.png)
![](https://i.imgur.com/YSyUTdt.jpg)
![](https://i.imgur.com/yc9Wjad.jpg)
![](https://i.imgur.com/0n7DZYa.jpg)
![](https://i.imgur.com/pijmdtO.jpg)
### P.324 Example 5.5
![](https://i.imgur.com/qlZtHOo.png)
![](https://i.imgur.com/UkClSVZ.png)
![](https://i.imgur.com/6UZXuf4.png)
### P.330 Example 5.8
![](https://i.imgur.com/YuYfTiq.png)
![](https://i.imgur.com/p9zOCtg.png)
![](https://i.imgur.com/PzBjYh6.png)
**Reference**
NCKUDPS 1101_Electronics(2)
Microelectronic Circuits 8/e by ADEL.S SEDRAc