---
# System prepended metadata

title: '講義(verilog, 0.安裝環境，測試4位元加法器電路)'
tags: [RISCV]

---

---
tags: RISCV
title: 講義(verilog, 0.安裝環境，測試4位元加法器電路)
---

[TOC]

# Enviroment setup

0. install WSL (ubuntu)
    > - [在Win11上安裝wsl2](https://hackmd.io/@hsueh945/HyzwaR4X3)
    > - [使用WSL2在Windows下快速打造Linux開發環境(含Docker)](https://ithelp.ithome.com.tw/articles/10255920)
    > - [自訂IP Address in WSL2](https://hackmd.io/@chtsai/rJ_vd6Y30)


1. crossed complie(Gcc)
> gcc 將在以後設計 riscv core時用來 compile 測試的程式檔。
2. verilator
> verilator 是用來將 verilog 檔轉換成 C++的物件及標頭檔，讓我們寫測試程式時可以使用所設計的硬體(轉成C++物件)
3. gtkwave
> gtkwave 用來觀看 模擬結果的時序圖
4. vscode
> vscode 編輯器用來編輯 verilog 及 測試程式

## install in ubuntu
1. install riscv gcc

> 推荐使用 Ubuntu 20.04以後的版本，安裝比較簡單。
```
$ lsb_release -a
No LSB modules are available.
Distributor ID:	Ubuntu
Description:	Ubuntu 20.04.3 LTS
Release:	20.04
Codename:	focal

$ uname -r
5.11.0-27-generic
```
> 目前在 Ubuntu 20.04 环境下我们可以直接使用官方提供的 GNU tools：
```
$ sudo apt update
$ sudo apt install build-essential gcc make perl dkms git gcc-riscv64-unknown-elf gdb-multiarch 
```

> install crossed compile in MS windows
> 

2. install verilator
```
https://ubuntu.pkgs.org/20.04/ubuntu-universe-arm64/verilator_4.028-1_arm64.deb.html

# sudo apt-get update
# sudo apt-get install verilator
```
> verilator install in MS Windows


3. install gtkwave
>gtkwave is a viewer for VCD (Value Change Dump) files which are usually created by digital circuit simulators

```
$ sudo apt-get update
$ sudo apt-get -y install gtkwave
```

<!--
> install gtkwave in windows
> https://gtkwave.sourceforge.net

4. install vscode
請自行上google 去找解


## install in MS Windows

https://www.msys2.org
:::success
Download and install MSYS2: https://sourceforge.net/projects/msys2/
Open MSYS2 shell and run 
```
pacman -Syu
```
After some time you will be prompted to close the MSYS2 shell by clicking the "X" button, which you should do :-)
Relaunch MSYS2 shell and run 
```
pacman -Su
```
Install the required packages for Verilator:
:::

> install help2man
```
pacman help2man
```

> install verilator
::: info
```bash=
> pacman -S git make autoconf gcc flex bison man perl python3
Clone the Verilator source and build the latest stable release:
> git clone http://git.veripool.org/git/verilator
> unset VERILATOR_ROOT
> cd verilator
> git checkout stable
> autoconf
> ./configure
> make
```

Test Verilator:
```
> make test
```
If the tests pass, install Verilator. Note that sudo is not used here since this is MSYS2, and that the PATH variable is updated so that the installer can find pod2man:
```
> PATH="/usr/bin/core_perl:${PATH}"
> make install
```
:::


> install gtkwave
:::success

```
> pacman -S mingw-w64-x86_64-gtkwave
```
:::

>install riscv toolchain
:::warning
```
pacman -S mingw-w64-x86_64-riscv64-unknown-elf-gcc
```
:::

> vscode 終端機使用 msys2 bash 請參考以下文章
https://hackmd.io/@VJ/vscodec

-->

# 設計的流程
## example 4bits 加法器

1. 使用 vscode 編輯 

![](https://i.imgur.com/k0agkVK.png)

```verilog=
module fulladder (
input a, b, c_in, 
output sum, c_out);

    wire s1, c1, c2;

    xor g1(s1, a, b);
    xor g2(sum, s1, c_in);
    and g3(c1, a,b);
    and g4(c2, s1, c_in) ;
    xor g5(c_out, c2, c1) ;

endmodule
```


![](https://i.imgur.com/cn9ovxJ.png)


```verilog=
module adder4(
    input signed [3:0] a, 
    input signed [3:0] b, 
    input c_in, 
    output signed [3:0] sum, 
    output c_out);

    wire [3:1] c;

    fulladder fa1(a[0],b[0], c_in, sum[0], c[1]) ;
    fulladder fa2(a[1],b[1], c[1], sum[1], c[2]) ;
    fulladder fa3(a[2],b[2], c[2], sum[2], c[3]) ;
    fulladder fa4(a[3],b[3], c[3], sum[3], c[4]) ;
;

endmodule
```

2. 如何使用 verilator 來模擬


![](https://hackmd.io/_uploads/SyTenO3B2.png)


---

> step1: 先產生一個 testbench file，等一下在修改內容
```C=
int main(){
}
```

> step 1: 執行 verilator 產生 top module的 C++ class and head files
```bash=
$ verilator adder4.v --exe testbench.cpp --cc
```
> 之後會產生一個 obj_dir 資料夾裡面包含了所有 adder4.v 轉換成 cpp的 class (Vadder4.cpp)
> head file (Vadder4.h), Makefile(Vadder4.mk）
![](https://i.imgur.com/u3lyfdF.jpg)

> step2:修改testbench.cpp

```C=
#include "Vadder4.h"
#include <memory>
#include <iostream>

int main(int, char**) {
        std::unique_ptr<Vadder4> dut(new Vadder4);

        dut->a=10;
        dut->b=4;
        dut->c_in=0;
        dut->eval();
        printf("%d\n", dut->sum);
        for(int i=0; i<16; i++) {
                dut->b = i;
                dut->eval();
                printf("%d\n", dut->sum);
        }
        return 0;
}

```

> step3. 產生 Vadder4 執行檔
```bash=
$ make -C obj_dir -f Vadder4.mk
```

> step4.執行產生的 模擬檔 Vadder4
```bash
$ ./obj_dir/Vadder4
14
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
```



4. 執行模擬程式後可產生 vcd檔，這可以用 gtkwave 看時序圖

> verilator 產生 wave file
> 1. 修改 testbench.cpp 如下
```C=
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include "Vadder4.h"
#include "verilated_vcd_c.h"

vluint64_t main_time = 0; 

double sc_time_stamp(int len)
 {
     return (main_time%len);
 }

int main(int argc,char **argv)
{
     Verilated::commandArgs(argc,argv);
     Verilated::traceEverOn(true); 

     VerilatedVcdC* tfp = new VerilatedVcdC(); 

     Vadder4 *top = new Vadder4("top");
     top->trace(tfp, 0);
     tfp->open("wave.vcd"); 

     while(sc_time_stamp(20) < 19 && !Verilated::gotFinish())
     {                                                                                                                          
        int a = rand() & 0xF;
        int b = rand() & 0xF;
        top->a = a;
        top->b = b;
        top->c_in=0;
        top->eval();
        printf("time=%ld, a = %d, b = %d, sum = %d\n",main_time, a,b, top->sum);
        tfp->dump(main_time); //dump wave
        main_time++; 
     }
     top->final();
     tfp->close();
     delete top;
     return 0;
}

```


```bash
$ verilator -Wall --cc --exe --build testbenchVCD.cpp adder4.v --trace
因為 --build 會直接make，產生 Vadder4 執行檔
$ ./obj_dir/Vadder4

產生 wave.vcd

$ gtkwave wave.vcd
```


![](https://i.imgur.com/SzIh8bv.png)



# verialtor vs Icarus verilog
> The two testing tools are:
1. Verilator using a C++ testbench.
2. Icarus Verilog using a Verilog testbench.

**A performance benchmark of testing unsigned multiplier Verilog of various size**
![](https://hackmd.io/_uploads/HJaDY8hHh.png)


# Home Work
```verilog=
module counter(input clk, rst, output reg [2:0] q);
    always @(posedge clk) begin
        if (rst)
            q <= 3'b000;
        else
            q <= q+1;
    end
endmodule
```

> 以上是一個簡單的計數器(counter)
> 請參考以上講義，利用 verilator 模擬，並產生vvd檔，用gtkwave看結果對不對。


# reference
> course source file t0 資料夾
> https://www.w3cschool.cn/verilog/verilog-rdio3o3b.html