Github : FreeRTOS-on-VexRiscv
Requirement and Expectation
:::warning
Reproduce Run FreeRTOS and multitasking on VexRiscv with FreeRTOS 202212.00 released or latest
Study Reference Link to understand how to measure FreeRTOS context switch
Understand how to accurately measure cycle count and related latencyInclude timer interrupt.
Run above at simulator and quantify the performence about context switch
作業說明
開發環境
$ gcc --version
gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ lscpu
contributed by < chiangkd >
開發環境
$ gcc --version
gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ lscpu
開發環境
$ gcc --version
gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
contributed by < chiangkd >
開發環境
$ gcc --version
gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ lscpu
contributed by < chiangkd >
開發環境
$ gcc --version
gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ lscpu
contributed by < chiangkd >
開發環境
$ gcc --version
gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0
Copyright (C) 2021 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ lscpu
contribute by <chiangkd>
Requirement follow Assignment3: SoftCPU
Source code
I choose the program from 鄒崴丞-Length of Last Word and Leetcode 77. Combinations
C code(Modified from 鄒崴丞)
#include <stdio.h>
contribute by <chiangkd>
Requirement follow Assignment2: RISC-V Toolchain
Pick up one Problem
Pick up one assembly program and adapt it into both RISC-V assembly and C implementations which can be flawlessly executed with rv32emu.
I choose the problem from 曾晧峖-Valid Anagram(Leetcode 242). The reason why I choose this problem is that when I go through the classmates homework from Assignment1: RISC-V Assembly and Instruction Pipeline. I notice that there is seldom problem is about string or character. I think only less than 5 problems is related. However, I want to know how string operation can efficiently run under RISC-V architecture.
contribyted by <chiangkd>
Requirements follow the assignment below:
Assignment1: RISC-V Assembly and Instruction Pipeline
Introduction
The problem I selected is Leetcode 82. Remove Duplicates from Sorted List II
Description