SystemVerilog Verification Using UVM
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Chapters (to be based on <UVM 1.2 User's Guide>)
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- [UVM Study](/qJ3hScyJRmWfs9PQmgmXCA)
- [UVM Sequence](/TKmV3hoKQP-CF0bsUfyPoQ)
- [UVM_EVENT_POOL](/gUcNZWbPQEeyU5xVFqNg0g)
- [UVM RAL](/3wshCcsDRBCX401-nfUy3w?both)
- [UVM Questions](/jAcZnPl-Rl68gmU2JcYcTQ)
# Know-how
## from SiFive
- `Config` should be centralized for easily debugging
- `sequence` should be executed in `body()`
Referenced codes
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- :notes: **Interview problem on `SiFive`:** [A simplified UVM TB for verifiying some opcode](https://www.edaplayground.com/x/cwH9)
- :notes: **Other completed UVM TB:** [APB](https://www.edaplayground.com/x/dUK)
- Debugging UVM environment: https://learnuvmverification.com/index.php/2016/05/22/debugging-uvm-environment/
Other studies
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- [Validation on RISC-V processor](/OIi8728QT1SQVQmZoubYqQ)
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