[TOC] # Lab 1 2nd Feb Basics of CMOS Technology NAND : pMOS in parallel { **remember by APP**, A : (N)AND, P : pMOS, P : parallel} Types of analysis Transient : calculates a circuit's response over a period of time defined by the user ## To calculate <ol> <li> Rise Time</li> <li> Fall Time</li> <li> Delay Time</li> </ol> ![diagram showing delay time and rise time](https://www.researchgate.net/publication/50219887/figure/fig1/AS:671527787843594@1537116109947/Delay-time-and-rising-time-for-a-step-input.png) Open LTSpice XVII Add component => serach for voltage Right click on the voltage component, click on advanced settings, and give the parameters to make the source V-pulse. Add components, R : 1kΩ ohm C : 1µF Connect components with wire, add a ground reference point. Right click on the schematic, create a Label Net, to observe voltage at a particular point. Click on the label-net, to observe the voltage trend. To compare the output with input, also create a label-net for the input side. ## Observations Peak Voltage 5V | timestamp | voltage | remarks | | -------- | -------- | - | | 1.71ms | 0.5V | Reaching V<sub>10</sub> at charging| | 23.41ms | 4.5V | Reaching V<sub>90</sub> at charging | | 102.56ms | 4.5V | Reaching V<sub>90</sub> at discharging| | 124.39ms | 0.5V | Reaching V<sub>10</sub> at discharging| # Lab 2 missed # Lab 3 16th Feb CMOS Create symbolic, schematic, merge and run # Lab 4 23rd Feb Transient and DC analysis for the following To create symbol 1. Hierarchy tab 2. Create new symbol | param | pulse 1 | pulse 2 | | - | - | - | | v_initial | 0 | 0| |Von |5 | 5 | |Tdelay |0|0| |Trise |0.001|0.001| |Tfall |0.001|0.001| |Ton |0.1|0.2| |Tperiod |0.2|0.4| ## NAND gate ### Schematic ![image](https://hackmd.io/_uploads/rJQpdhSna.png) <hr> ### Truth Table | A | B | Output | |-|-|-| |0|0|1| |0|1|1| |1|0|1| |1|1|0| <hr> ## NOR gate pMOS in series, nMOS in parallel ### Schematic ![image](https://hackmd.io/_uploads/rJQBtnS3a.png) ### Truth Table | A | B | Output | |-|-|-| |0|0|1| |0|1|0| |1|0|0| |1|1|0| # Lab 5 8th March ## XOR ### Schematic ![XOR Gate schematic from allaboutelectronics](https://hackmd.io/_uploads/r1fnamdap.png) ### Truth Table | A | B | Output | |-|-|-| |0|0|0| |0|1|1| |1|0|1| |1|1|0| ## XNOR ### Schematic ![image](https://hackmd.io/_uploads/ryjCnQu6T.png) ### Truth Table | A | B | Output | |-|-|-| |0|0|1| |0|1|0| |1|0|0| |1|1|1| # Lab 6 15th March MuX 4x1 MuX using CMOS 2x1 MuX using CMOS ![image](https://hackmd.io/_uploads/BklAcvZ0a.png) To create 4x1 MuX using 2x1 # Lab 9 12th April # Viva Questions Why to use CMOS technology ? 1. Less power dissipation 2. Compact, saves space 3. Large noise tolerance When to prefer BJT over CMOS ? Faster speeds, as in CMOS