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Lab 1 2nd Feb

Basics of CMOS Technology
NAND : pMOS in parallel { remember by APP, A : (N)AND, P : pMOS, P : parallel}

Types of analysis
Transient : calculates a circuit's response over a period of time defined by the user

To calculate

  1. Rise Time
  2. Fall Time
  3. Delay Time

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Open LTSpice XVII

Add component => serach for voltage
Right click on the voltage component, click on advanced settings, and give the parameters to make the source V-pulse.

Add components, R : 1kΩ ohm C : 1µF
Connect components with wire, add a ground reference point.

Right click on the schematic, create a Label Net, to observe voltage at a particular point.

Click on the label-net, to observe the voltage trend. To compare the output with input, also create a label-net for the input side.

Observations

Peak Voltage 5V

timestamp voltage remarks
1.71ms 0.5V Reaching V10 at charging
23.41ms 4.5V Reaching V90 at charging
102.56ms 4.5V Reaching V90 at discharging
124.39ms 0.5V Reaching V10 at discharging

Lab 2 missed

Lab 3 16th Feb

CMOS

Create symbolic, schematic, merge and run

Lab 4 23rd Feb

Transient and DC analysis for the following

To create symbol

  1. Hierarchy tab
  2. Create new symbol
param pulse 1 pulse 2
v_initial 0 0
Von 5 5
Tdelay 0 0
Trise 0.001 0.001
Tfall 0.001 0.001
Ton 0.1 0.2
Tperiod 0.2 0.4

NAND gate

Schematic

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Truth Table

A B Output
0 0 1
0 1 1
1 0 1
1 1 0

NOR gate

pMOS in series, nMOS in parallel

Schematic

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Truth Table

A B Output
0 0 1
0 1 0
1 0 0
1 1 0

Lab 5 8th March

XOR

Schematic

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Truth Table

A B Output
0 0 0
0 1 1
1 0 1
1 1 0

XNOR

Schematic

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Truth Table

A B Output
0 0 1
0 1 0
1 0 0
1 1 1

Lab 6 15th March MuX

4x1 MuX using CMOS

2x1 MuX using CMOS

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To create 4x1 MuX using 2x1

Lab 9 12th April

Viva Questions

Why to use CMOS technology ?

  1. Less power dissipation
  2. Compact, saves space
  3. Large noise tolerance

When to prefer BJT over CMOS ?
Faster speeds, as in CMOS