# WiFi 6/7 Software-Defined Radio Design Report

## Executive Summary

This report outlines the minimum hardware requirements and architecture for building an open-source WiFi 6 (802.11ax) and WiFi 7 (802.11be) radio using FPGA-based baseband processing and commercial RF frontend components.

**Target:** miniPCI-e or M.2 form factor WiFi card with open-source baseband (OpenWiFi)

**Estimated Cost:** ~$120-205 (qty 100)

## Nice to read
https://media.ccc.de/v/gpn22-380-how-a-wifi-chip-works-internally

https://wiki.f-si.org/images/a/ad/Openwifi.pdf.pdf
https://archive.fosdem.org/2022/schedule/event/radio_openwifi/attachments/slides/5181/export/events/attachments/radio_openwifi/slides/5181/openwifi_fosdem2022_simple.pdf

**Wifi sdr**
https://www.nuand.com/bladerf-wiphy/
https://arxiv.org/html/2501.06176v1 GR_Wifi
https://github.com/cloud9477/gr-ieee80211
https://www.ccs.neu.edu/home/vohuudtr/publications/swifi.pdf

https://www.crowdsupply.com/microphase-technology/antsdr-e200 +330u$s
https://github.com/MicroPhase/antsdr_uhd

https://www.qorvo.com/design-hub/blog/how-not-to-run-hot-overcoming-thermal-challenges-in-wifi-front-end-designs
https://www.qorvo.com/design-hub/blog/resolving-interference-in-a-crowded-wifi-environment-using-baw-filters
https://www.qorvo.com/-/media/files/qorvopublic/ebooks/qorvo-rf-filter-technology-for-dummies-qorvo-2nd-special-edition.pdf

https://limemicro.com/systems/ provides 4Gand 5G solutions with own SOCs and SDRs ...
https://github.com/srsran/srsRAN_4G

https://github.com/bastibl/gr-ieee802-11

https://www.zeroasic.com/blog/wildebeest-launch

https://blog.quarkslab.com/reverse-engineering-broadcom-wireless-chipsets.html

https://mangocomm.com/802.11-mac-phy/ MAX2829 con ADC ejemplo WARP v3

## Definitions
Standards Wi-Fi **WiFi7**:be, WiFi6**:ax, **WiFi5**:ac

**Power Amplifiers (PAs):** Components that increase the power of a
radio signal for transmission.

**Switches**: Used to route RF signals between different paths in a
circuit.

**Filters**: Components that selectively allow signals within a desired
frequency range to pass while suppressing others

**LNA**: Low noise amplifier

### Digital Baseband

The **digital baseband** is the signal processing core that transforms binary data into radio-ready signals (TX) and vice versa (RX).

**TX Path:**
Data bits → Encoding → Interleaving → OFDM Modulation →
IFFT → Add Preambles → I/Q Digital → DAC → RF

**RX Path:**
RF → ADC → I/Q Digital → Synchronization → FFT →
Equalization → OFDM Demodulation → Deinterleaving →
Decoding → Data bits

**Components:**
- OFDM Modulator/Demodulator
- FFT/IFFT engines
- Viterbi/LDPC decoder (Forward Error Correction)
- AGC (Automatic Gain Control)
- Timing & frequency synchronization
- Channel estimation

**I/Q (In-phase/Quadrature)** represents complex RF signals as two baseband components:

- **I (In-phase):** Real component, 0° phase
- **Q (Quadrature):** Imaginary component, 90° phase
**Two Types:**

| Type | Description | Requires ADC/DAC | Used By |
|------|-------------|------------------|---------|
| **Analog I/Q** | Continuous voltage signals (±1V differential) | ✅ Yes (external) | MAX2829, RFX2401C |
| **Digital I/Q** | LVDS digital samples (12-bit words) | ❌ No (integrated) | ADRV9002, AD9361 |


### RF Frontend Components
**Front-End Modules (FEMs)**: These are integrated solutions that
combine several RF functions (like power amplifiers, switches, filters,
and low-noise amplifiers) for a complete radio system in a single
package.

Integrated module containing:
- **PA (Power Amplifier):** Boosts TX signal to +20dBm
- **LNA (Low Noise Amplifier):** Amplifies weak RX signal (+15dB)
- **T/R Switch:** Routes signal between TX and RX paths
- **Optional:** Power detector, coupler, filters

**What FEM does NOT do:**
- ❌ Frequency conversion (mixing)
- ❌ Local oscillator generation
- ❌ I/Q modulation/demodulation
- ❌ Baseband processing

#### Transceiver
Complete RF conversion engine:
- **Upconverter (TX):** I/Q baseband → RF (2.4/5/6 GHz)
- **Downconverter (RX):** RF → I/Q baseband
- **VCO/PLL:** Frequency synthesizer
- **Optional:** Integrated ADC/DAC

### WiFi 6 vs WiFi 7 Requirements

| Feature | WiFi 4 (11n) | WiFi 6 (11ax) | WiFi 7 (11be) |
|---------|--------------|---------------|---------------|
| **Bandwidth** | 20/40 MHz | 20/40/80/160 MHz | 320 MHz |
| **Modulation** | up to 64-QAM | **1024-QAM** | **4096-QAM** |
| **OFDMA** | No | ✅ Yes | ✅ Yes |
| **MU-MIMO** | SU-MIMO | 8x8 | 16x16 |
| **Frequency Bands** | 2.4/5 GHz | 2.4/5/6 GHz | 2.4/5/6 GHz |
| **EVM Required** | -25 dB | **-35 dB** | **-40 dB** |

**Key Implications:**
- WiFi 6 requires better linearity than WiFi 4/5
- WiFi 7 needs wider bandwidth (320 MHz) - challenging for current SDR hardware
- 6 GHz band support essential for WiFi 6E/7

---
# WIFI SDR
## OpenWifi

Uses AD9361 is a highly integrated RF Agile Transceiver from Analog Devices, it seems it is not using amplifiers.

All the platforms OpenWifi currently use have fair big FPGA on board. However the HackRF, BladeRF, LImeSDR only have quite small FPGA on board.

Openwifi implements not only CSMA/CA on FPGA, but also full physical layer signal processing ( OFDM modulation, demodulation, etc) on FPGA. The reason why we implement all functionalities of Low MAC and layer below on FPGA is because of SIFS:
https://en.wikipedia.org/wiki/Short_Interframe_Space


# Open-Source WiFi SDR Projects: Comparative Analysis

This section compares thre major open-source WiFi Software-Defined Radio projects with OpenWiFi, analyzing their architectures, capabilities, and suitability for WiFi 6/7 development.

| Project | Platform | WiFi Standard | Implementation | MIMO | Open Source Level |
|---------|----------|---------------|----------------|------|-------------------|
| **OpenWiFi** | FPGA (Zynq) | 802.11a/g/n | FPGA HDL | 2x2 | Full (AGPL) |
| **bladeRF-wiphy** | FPGA (Altera) | 802.11a/g | FPGA VHDL | 1x1 | Full (GPL) |
| **GR-WiFi** | GNU Radio/USRP | 802.11a/g/n/ac | Software (C++) python| 2x2 SU/MU-MIMO | Full (open) |

**bladeRF-wiphy Technical Highlights:**

# Design Improvement to reduce cost
Looking into antsdr (the cheapest openwifi supported hw) the main costs are fpga and tranceiver so:
1. Use smaller fpga, use external micro controller ?
2. Use cheap radio hardware les flexible, dont want an sdr, need some wifi specific tranceiver
3.
This wolud requiere hard reimplementation of part of the openwifi platform.

## 2. Component Selection Analysis

### 2.1 Transceiver Options Comparison

| Component | Type | Freq Range | BW Max | ADC/DAC | Channels | Price | WiFi 6 | WiFi 7 |
|-----------|------|------------|--------|---------|----------|-------|--------|--------|
| **MAX2829** | Analog I/Q | 2.4/5 GHz | 40 MHz | ❌ External | 1 TX/RX | $26.35 | ⚠️ Limited | ❌ No |
| **ADRV9002**+ | Digital I/Q | 30M-6G | 40 MHz | ✅ 12-bit | 2x2 MIMO | $294 | ✅ Yes | ⚠️ Partial |
| **LMS7002M** ++ | Digital I/Q | 0.1-3.8G | 120 MHz | ✅ 12-bit | 2x2 MIMO | $131 | ⚠️ 2.4G only | ❌ No |
| **AD9361** | Digital I/Q | 70M-6G | 56 MHz | ✅ 12-bit | 2x2 MIMO | $224 | ✅ Yes | ⚠️ Partial |
|**AD9363** | Digital I/Q | 70M-6G | 56 MHz | ✅ 12-bit | 2x2 MIMO | $102,72 | ✅ Yes | ⚠️ Partial |

**Notes:**
- + = Recommended
- ++ = Can be used in 5G with another component
- MAX2829 requires external ADC ($8) + DAC ($12) = total ~$30 maight be implemented in fpga ?
- MAX maight be capable of achieving 1024 QAM but wont be able handle multiple mimo without nother MAX
- WiFi 7 (320 MHz) not fully achievable with current affordable transceivers

#### USE ADRV9002

Replacing the **AD9361** with the **ADRV9002** can **significantly reduce the requirements on the FPGA's Digital Signal Processing (DSP) logic and overall complexity**, but it may **increase the demand on the FPGA's high-speed I/O (SerDes)** resources.

Here's a breakdown of the impact:

***

###### 1. Reduction in FPGA DSP Logic Requirements (The Benefit)

The ADRV9002 integrates more digital baseband processing functions internally than the AD9361, which **offloads** the FPGA from having to perform these standard tasks.

| Function | AD9361 Status | **ADRV9002 Status** | FPGA Impact (ADRV9002) |
| :--- | :--- | :--- | :--- |
| **DC Offset Correction** | Requires FPGA intervention | **Fully Integrated** | **Reduces** FPGA DSP logic and software complexity. |
| **Quadrature Error Correction (QEC)** | Requires FPGA intervention | **Fully Integrated** | **Reduces** FPGA DSP logic and requires less complex calibration logic. |
| **Programmable Digital Filters** | Integrated, but less flexible | **Integrated and Flexible** | **Reduces** the need for complex filter logic (e.g., polyphase filters) on the FPGA fabric. |
| **Digital Pre-Distortion (DPD)** | Not integrated | **Fully Integrated** | **Eliminates** the need for a high-complexity, real-time DPD engine on the FPGA. This is a massive resource saving, especially for high-linearity WiFi 6/7. |

**Conclusion on Baseband:** The ADRV9002 allows the OpenWiFi platform to use the FPGA to focus almost entirely on the core **MAC/PHY** (OFDM/OFDMA, FFT/IFFT, LDPC, and SIFS timing), freeing up resources previously dedicated to analog signal correction.

***

###### 2. Potential Increase in FPGA I/O Requirements (The Trade-Off)

The ADRV9002 features a newer, higher-speed digital interface which can change the type of FPGA needed.

| Feature | AD9361 | **ADRV9002** | FPGA Impact (ADRV9002) |
| :--- | :--- | :--- | :--- |
| **Max Bandwidth (BW)** | $\sim 56 \text{ MHz}$ | $\sim 40 \text{ MHz}$ | **Note:** The ADRV9002's max BW of $40\text{ MHz}$ is **too low** for **WiFi 6/7** ($160\text{ MHz}/320\text{ MHz}$). For true WiFi 6/7, a transceiver like the $\text{ADRV9009}$ or similar wideband part that uses $\text{JESD204B}$ is required. |
| **Digital Interface** | **LVDS** (Parallel/Low-speed Serial) | **LVDS or CMOS Synchronous Serial Interface (SSI)** | LVDS interfaces are generally easier to implement but require a high number of General Purpose I/O (GPIO) pins. |
| **Higher-End Alternative (e.g., ADRV9009)** | N/A | **JESD204B** (High-speed Serial) | JESD204B requires the FPGA to have **dedicated high-speed serial transceivers (SerDes)**, which are only found on mid-to-high-end FPGAs (like Xilinx Artix-7/Zynq or Intel Cyclone V/Stratix families). This feature often drives up the FPGA cost and complexity compared to simple LVDS. |

**Overall Impact:**

1. **DSP Logic:** The ADRV9002 **reduces** the complexity required in the FPGA's main logic fabric.
2. **I/O:** While the base ADRV9002 may not be sufficient for the required $\text{160 MHz/320 MHz}$ WiFi bandwidth, any transceiver capable of that bandwidth (the true requirement for this project) will require a modern **JESD204B** interface, which necessitates a more advanced, higher-end $\text{FPGA}$ with $\text{SerDes}$ blocks.

Therefore, while the **ADRV9002** reduces the **logic requirements** (making the code/design simpler), meeting the **WiFi 6/7 bandwidth** will force the use of a wideband chip that requires an $\text{FPGA}$ with **more expensive high-speed I/O capability.**

### 2.2 Frontend Module Options (Skyworks)

#### WiFi 6 FEM Components

| Component | Band | WiFi Std | Features | Price |
|-----------|------|----------|----------|-------|
| **SKY85354-11** | 2.4 GHz | WiFi 6 | PA +20dBm, LNA, Switch, Coupler | $3-5 |
| **SKY85331-11** | 2.4 GHz | WiFi 6 | High-power PA, LNA, Switch | $4-6 |
| **SKY85746-11** | 5 GHz | WiFi 6 | Ultra-linear PA +21dBm, LNA, Log detector | $5-7 |
| **SKY85747-11** | 5 GHz | WiFi 6 | High-power PA, LNA, Switch | $5-7 |
| **SKY85780-11** | 6 GHz | WiFi 6E | PA, LNA, Switch for 6GHz band | $6-8 |

#### WiFi 7 Ready FEM Components

| Component | Band | WiFi Std | Features | Price |
|-----------|------|----------|----------|-------|
| **SKY85791-11** | 5 GHz | WiFi 7 | PA, LNA, Switch, DPD Coupler | $6-8 |
| **SKY85784-11** | 6 GHz | WiFi 6E/7 | High-power 6GHz FEM | $6-8 |

**Key Points:**
- All FEM modules require external transceiver
- FEMs simplify PA/LNA design significantly
- WiFi 6/7 FEMs optimized for higher linearity (1024-QAM+)

### 2.3 FPGA Selection

| FPGA | Logic Cells | DSP Slices | RAM | ARM Cores | Price | Use Case |
|------|-------------|------------|-----|-----------|-------|----------|
| **Zynq-7010** | 28K | 80 | 240KB | Dual A9 | $50 | 2.4GHz only, basic |
| **Zynq-7020** | 85K | 220 | 560KB | Dual A9 | $80 | Full WiFi 6, dual-band |
| **Zynq-7035** | 275K | 900 | 1.8MB | Dual A9 | $200+ | Overkill for WiFi |

**OpenWiFi Requirements:**
- ~20K LUTs
- 110 DSP slices
- 75 BRAM blocks
- ⭐ Zynq-7020 recommended for production design

---

### 3.1 WiFi 6 Dual-Band Configuration (Recommended)

#### Bill of Materials

| # | Component | Function | Specifications | Qty | Unit Price | Total |
|---|-----------|----------|----------------|-----|------------|-------|
| **RF Frontend - 2.4 GHz** |
| 1 | SKY85354-11 | FEM 2.4G | PA +20dBm, LNA 15dB, Switch | 1 | $4 | $4 |
| 2 | SAW Filter 2.4G | Bandpass filter | 2400-2500 MHz, IL<2dB | 2 | $1.50 | $3 |
| **RF Frontend - 5 GHz** |
| 3 | SKY85746-11 | FEM 5G | PA +21dBm, LNA 14dB, Log det | 1 | $6 | $6 |
| 4 | SAW Filter 5G | Bandpass filter | 5150-5850 MHz, IL<2.5dB | 2 | $2 | $4 |
| **Transceiver** |
| 5 | ADRV9002 | RF Transceiver | 30MHz-6GHz, 12-bit ADC/DAC, 2x2 | 1 | $30 | $30 |
| **Digital Processing** |
| 6 | Zynq-7020 | FPGA + ARM | XC7Z020, Dual Cortex-A9 | 1 | $80 | $80 |
| 7 | DDR3 RAM | Memory | 512MB, MT41K256M16 | 1 | $5 | $5 |
| **Clock & Reference** |
| 8 | TCXO 40MHz | Reference osc | ±2.5ppm, Vectron VT-803 | 1 | $2 | $2 |
| 9 | Si5351 | Clock generator | Multi-output PLL | 1 | $2 | $2 |
| **Power Supply** |
| 10 | DC-DC Buck | 5V→1.0V | 3A for FPGA core | 1 | $3 | $3 |
| 11 | LDO 3.3V | Linear reg | 1A, low noise for RF | 2 | $1 | $2 |
| 12 | LDO 1.8V | Linear reg | 500mA for I/O | 1 | $1 | $1 |
| **Passives & Connectors** |
| 13 | Capacitors | Bypass/coupling | 0402/0603, 100+ pcs | 1 | $8 | $8 |
| 14 | Resistors | Bias/matching | 0402, 50+ pcs | 1 | $2 | $2 |
| 15 | Inductors | RF matching | 0603/0805, 20+ pcs | 1 | $5 | $5 |
| 16 | U.FL connectors | Antenna ports | 2x for dual-band | 2 | $1 | $2 |
| 17 | PCIe edge conn | Host interface | miniPCI-e or M.2 | 1 | $3 | $3 |
| **PCB** |
| 18 | PCB 6-layer | Substrate | 80x50mm, controlled impedance | 1 | $25 | $25 |
| | | | | | **TOTAL** | **$187** |

#### Cost Breakdown by Subsystem

| Subsystem | Components | Cost | Percentage |
|-----------|-----------|------|------------|
| RF Frontend | FEMs + SAW filters | $17 | 9% |
| Transceiver | ADRV9002 | $30 | 16% |
| Digital Processing | Zynq + DDR3 | $85 | 45% |
| Clock/Reference | TCXO + Si5351 | $4 | 2% |
| Power | DC-DC + LDOs | $6 | 3% |
| Passives | Caps, res, ind | $15 | 8% |
| Mechanical | Connectors | $5 | 3% |
| PCB | 6-layer board | $25 | 13% |

### 3.2 WiFi 7 Ready Configuration (Tri-Band)

**Additional Components for WiFi 7:**

| Component | Reason | Price |
|-----------|--------|-------|
| SKY85791-11 (5GHz) | WiFi 7 optimized FEM with DPD | $7 |
| SKY85780-11 (6GHz) | 6GHz band support (WiFi 6E/7) | $7 |
| SAW Filters 6GHz | Bandpass for 6GHz | $3 |

**WiFi 7 Total:** ~$204 (adds $17 for 6GHz support)

**Limitations:**
- ⚠️ Current transceivers limited to 40-56 MHz instantaneous BW
- ⚠️ WiFi 7 requires 320 MHz → need bandwidth stitching or future hardware
- ⚠️ 4096-QAM requires EVM <-40dB → challenging but achievable

### Transceivers Diseñados para FPGA/SDR**

**Estos son los MÁS RELEVANTES para tu proyecto:**

| Chip | Fabricante | Frecuencias | Bandwidth | Interfaz Digital | ADC/DAC | Precio (qty 100) | Precio (qty 1000) |
|------|-----------|-------------|-----------|------------------|---------|-------------------|-------------------|
| **AD9363** | Analog Devices | 325 MHz - 3.8 GHz | Hasta 20 MHz | LVDS/CMOS | 12-bit integrado | ~$45-60 | ~$35-45 |
| **AD9364** | Analog Devices | 70 MHz - 6 GHz | Hasta 56 MHz | LVDS/CMOS | 12-bit integrado | ~$90-120 | ~$70-90 |
| **ADRV9002** | Analog Devices | 30 MHz - 6 GHz | Hasta 40 MHz | SPI Control | 12-bit integrado | ~$25-35 | ~$18-25 |
| **LMS7002M** | Lime Microsystems | 100 kHz - 3.8 GHz | Hasta 120 MHz | SPI/I2C | 12-bit integrado | ~$30-40 | ~$22-30 |

### **OPCIÓN ADRV9002**

┌──────────────────────────────────────────────────┐
│         BOM para WiFi 6 (Dual Band)              │
├──────────────────────────────────────────────────┤
│ 1. ADRV9002 (RF + ADC/DAC)          $30         │
│ 2. Skyworks SKY85354-11 (2.4G FEM)  $4          │
│ 3. Skyworks SKY85746-11 (5G FEM)    $6          │
│ 4. Zynq-7020 FPGA                   $80         │
│ 5. TCXO 40MHz   ???                 $2          │
│ 6. DDR3 RAM 512MB                   $5          │
│ 7. SAW Filters                      $7          │
│ 8. Power supplies                   $6          │
│ 9. Pasivos + Conectores             $20         │
│ 10. PCB (miniPCI/M.2)               $25         │
├──────────────────────────────────────────────────┤
│ TOTAL:                              ~$185       │
└──────────────────────────────────────────────────┘

FEM are important to achieve

## Alternativa Económica (Solo 2.4 GHz)

┌──────────────────────────────────────────────────┐
│    BOM Ultra-Económico (Solo 2.4 GHz)            │
├──────────────────────────────────────────────────┤
│ 1. LMS7002M (RF + ADC/DAC)          $25         │
│ 2. Skyworks SKY85354-11 (2.4G FEM)  $4          │
│ 3. Zynq-7010 FPGA (más chico)       $50         │
│ 4. TCXO 40MHz                       $2          │
│ 5. DDR3 RAM 256MB                   $3          │
│ 6. SAW Filter 2.4G                  $3          │
│ 7. Power supplies                   $5          │
│ 8. Pasivos + Conectores             $15         │
│ 9. PCB (miniPCI)                    $20         │
├──────────────────────────────────────────────────┤
│ TOTAL:                              ~$127       │
└──────────────────────────────────────────────────┘

---

Poblems: LMS7002M and ADRV9002 are not supported by openwifi
ADRV9002