---
title: /RRH/開發
tags: rrh
description: RRH booting
---
# RU booting log
```
U-Boot 2014.10-00320-g077e579-dirty (Apr 16 2017 - 22:35:05)
CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
FPGA: writing ghrd_10as066n2.periph.rbf ...
FPGA: Early Release Succeeded.
DDRCAL: Success
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe386e8
DRAM : 1 GiB
WARNING: Caches not enabled
MMC: In: serial
Out: serial
Err: serial
Model: SOCFPGA Arria10 Dev Kit
Net: dwmac.ff800000
Hit any key to stop autoboot: 0
FPGA: writing ghrd_10as066n2.core.rbf ...
Full Configuration Succeeded.
** Unable to read file u-boot.scr **
4799192 bytes read in 233 ms (19.6 MiB/s)
23945 bytes read in 4 ms (5.7 MiB/s)
FPGA BRIDGES: enable
Kernel image @ 0x008000 [ 0x000000 - 0x493ad8 ]
## Flattened Device Tree blob at 00000100
Booting using the fdt blob at 0x000100
Loading Device Tree to 01ff7000, end 01fffd88 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 5.2.0-rc3-g4b574d3-dirty (joanne@faca-l1sw0) (gcc 0
[ 0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instructie
[ 0.000000] OF: fdt: Machine model: Altera SOCFPGA Arria 10
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] percpu: Embedded 19 pages/cpu s48704 r8192 d20928 u77824
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260608
[ 0.000000] Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p2 rwt
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 1027396K/1048576K available (8192K kernel code, 536K rwd)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[ 0.000000] ftrace: allocating 26792 entries in 53 pages
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 ji.
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] L2C-310 erratum 769419 enabled
[ 0.000000] L2C-310 enabling early BRESP for Cortex-A9
[ 0.000000] L2C-310: enabling full line of zeros but not enabled in Cortex-A9
[ 0.000000] L2C-310 ID prefetch enabled, offset 1 lines
[ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[ 0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
[ 0.000000] L2C-310: CACHE_ID 0x410030c9, AUX_CTRL 0x76460001
[ 0.000000] random: get_random_bytes called from start_kernel+0x314/0x4bc wi0
[ 0.000000] GIC: PPI13 is secure or misconfigured
[ 0.000000] GIC: PPI13 is secure or misconfigured
[ 0.000000] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, maxs
[ 0.000004] sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 4294s
[ 0.000010] Switching to timer-based delay loop, resolution 20ns
[ 0.000225] Console: colour dummy device 80x30
[ 0.000249] Calibrating delay loop (skipped), value calculated using timer f)
[ 0.000258] pid_max: default: 32768 minimum: 301
[ 0.000351] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000359] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000705] *** VALIDATE proc ***
[ 0.000799] *** VALIDATE cgroup1 ***
[ 0.000806] *** VALIDATE cgroup2 ***
[ 0.000813] CPU: Testing write buffer coherency: ok
[ 0.000833] CPU0: Spectre v2: using BPIALL workaround
[ 0.000837] SHARE_MEM: start to init share mem
[ 0.000848] SHARE_MEM: address of share_mem1 0xef100000
[ 0.000852] SHARE_MEM: physical address is 0x2f100000
[ 0.000906] SHARE_MEM for bigger bin: address is 0xee800000
[ 0.000909] SHARE_MEM for bigger bin: physical address is 0x2e800000
[ 0.001099] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.001398] Setting up static identity map for 0x100000 - 0x100060
[ 0.001493] rcu: Hierarchical SRCU implementation.
[ 0.001688] smp: Bringing up secondary CPUs ...
[ 0.001991] smp: Brought up 1 node, 1 CPU
[ 0.001999] SMP: Total of 1 processors activated (100.00 BogoMIPS).
[ 0.002004] CPU: All CPU(s) started in SVC mode.
[ 0.002728] devtmpfs: initialized
[ 0.005755] VFP support v0.3: implementor 41 architecture 3 part 30 variant 4
[ 0.005892] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ms
[ 0.005907] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.006520] NET: Registered protocol family 16
[ 0.007076] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.007676] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint.
[ 0.007683] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.016692] gpio gpiochip2: (/sopc@0/bridge@0xc0000000/gpio@0x100000030): de.
[ 0.016977] vgaarb: loaded
[ 0.017167] SCSI subsystem initialized
[ 0.017294] usbcore: registered new interface driver usbfs
[ 0.017321] usbcore: registered new interface driver hub
[ 0.017362] usbcore: registered new device driver usb
[ 0.017478] usb_phy_generic sopc@0:usbphy0: sopc@0:usbphy0 supply vcc not for
[ 0.018093] pps_core: LinuxPPS API ver. 1 registered
[ 0.018100] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giom>
[ 0.018111] PTP clock support registered
[ 0.018218] FPGA manager framework
[ 0.018814] clocksource: Switched to clocksource timer
[ 0.271478] NET: Registered protocol family 2
[ 0.271891] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144)
[ 0.271910] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.271966] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.272050] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.272150] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.272195] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.272354] NET: Registered protocol family 1
[ 0.272762] RPC: Registered named UNIX socket transport module.
[ 0.272769] RPC: Registered udp transport module.
[ 0.272773] RPC: Registered tcp transport module.
[ 0.272777] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.272786] PCI: CLS 0 bytes, default 64
[ 0.273217] hw perfevents: no interrupt-affinity property for /sopc@0/pmu0, .
[ 0.273358] hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 countee
[ 0.274152] workingset: timestamp_bits=30 max_order=18 bucket_order=0
[ 0.278646] NFS: Registering the id_resolver key type
[ 0.278675] Key type id_resolver registered
[ 0.278679] Key type id_legacy registered
[ 0.278690] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[ 0.279171] ntfs: driver 2.1.32 [Flags: R/W].
[ 0.279363] jffs2: version 2.2. (NAND) �© 2001-2006 Red Hat, Inc.
[ 0.279921] bounce: pool size: 64 pages
[ 0.279935] io scheduler mq-deadline registered
[ 0.279940] io scheduler kyber registered
[ 0.283715] dma-pl330 ffda1000.dma: Loaded driver for PL330 DMAC-341330
[ 0.283728] dma-pl330 ffda1000.dma: DBUFF-512x8bytes Num_Chans-8 Num_Peri-38
[ 0.285680] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[ 0.286412] printk: console [ttyS0] disabled
[ 0.286442] ffc02100.serial: ttyS0 at MMIO 0xffc02100 (irq = 30, base_baud =A
[ 0.909569] printk: console [ttyS0] enabled
[ 0.914757] brd: module loaded
[ 0.923296] loop: module loaded
[ 0.927715] at24 0-0051: 4096 byte 24c32 EEPROM, writable, 32 bytes/write
[ 0.935777] libphy: Fixed MDIO Bus: probed
[ 0.940275] CAN device driver interface
[ 0.944363] socfpga-dwmac ff800000.ethernet: PTP uses main clock
[ 0.950538] socfpga-dwmac ff800000.ethernet: User ID: 0x10, Synopsys ID: 0x37
[ 0.957645] socfpga-dwmac ff800000.ethernet: DWMAC1000
[ 0.962866] socfpga-dwmac ff800000.ethernet: DMA HW capability register suppd
[ 0.970322] socfpga-dwmac ff800000.ethernet: RX Checksum Offload Engine suppd
[ 0.977769] socfpga-dwmac ff800000.ethernet: COE Type 2
[ 0.982976] socfpga-dwmac ff800000.ethernet: TX Checksum insertion supported
[ 0.989997] socfpga-dwmac ff800000.ethernet: Enhanced/Alternate descriptors
[ 0.996925] socfpga-dwmac ff800000.ethernet: Enabled extended descriptors
[ 1.003685] socfpga-dwmac ff800000.ethernet: Ring mode enabled
[ 1.009498] socfpga-dwmac ff800000.ethernet: Enable RX Mitigation via HW Watr
[ 1.024807] libphy: stmmac: probed
[ 1.028203] Micrel KSZ9031 Gigabit PHY stmmac-0:07: attached PHY driver [Mic)
[ 1.041678] dwc2 ffb00000.usb: ffb00000.usb supply vusb_d not found, using dr
[ 1.049999] dwc2 ffb00000.usb: ffb00000.usb supply vusb_a not found, using dr
[ 1.058456] dwc2 ffb00000.usb: dwc2_core_reset: HANG! AHB Idle timeout GRSTCE
[ 1.067180] dwc2: probe of ffb00000.usb failed with error -16
[ 1.073024] usbcore: registered new interface driver usb-storage
[ 1.079536] rtc-ds1307: probe of 0-0068 failed with error -121
[ 1.085373] i2c /dev entries driver
[ 1.089514] Synopsys Designware Multimedia Card Interface Driver
[ 1.095697] dw_mmc ff808000.flash: IDMAC supports 32-bit address mode.
[ 1.102260] dw_mmc ff808000.flash: Using internal DMA controller.
[ 1.108331] dw_mmc ff808000.flash: Version ID is 270a
[ 1.113404] dw_mmc ff808000.flash: DW MMC controller at irq 34,32 bit host do
[ 1.122573] mmc_host mmc0: card is polling.
[ 1.138814] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000H)
[ 1.159005] ledtrig-cpu: registered to indicate activity on CPUs
[ 1.165093] usbcore: registered new interface driver usbhid
[ 1.170657] usbhid: USB HID core driver
[ 1.174740] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered
[ 1.181659] oprofile: using arm/armv7-ca9
[ 1.186205] NET: Registered protocol family 10
[ 1.191293] Segment Routing with IPv6
[ 1.195014] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 1.201335] NET: Registered protocol family 17
[ 1.205772] NET: Registered protocol family 15
[ 1.210219] can: controller area network core (rev 20170425 abi 9)
[ 1.216408] NET: Registered protocol family 29
[ 1.220845] can: raw protocol (rev 20170425)
[ 1.225093] can: broadcast manager protocol (rev 20170425 t)
[ 1.230734] can: netlink gateway (rev 20170425) max_hops=1
[ 1.236316] 8021q: 802.1Q VLAN Support v1.8
[ 1.240521] Key type dns_resolver registered
[ 1.244822] ThumbEE CPU extension supported.
[ 1.249093] Registering SWP/SWPB emulation handler
[ 1.256130] hctosys: unable to open rtc device (rtc0)
[ 1.261621] ttyS0 - failed to request DMA
[ 1.265783] Waiting for root device /dev/mmcblk0p2...
[ 1.300928] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 5000000)
[ 1.310674] mmc0: new high speed SDHC card at address 0007
[ 1.317043] mmcblk0: mmc0:0007 SD16G 14.4 GiB
[ 1.323002] mmcblk0: p1 p2 p3
[ 1.330420] EXT4-fs (mmcblk0p2): mounting ext3 file system using the ext4 sum
[ 1.391614] random: fast init done
[ 2.643806] random: crng init done
[ 2.881070] EXT4-fs (mmcblk0p2): warning: maximal mount count reached, runnid
[ 2.900857] EXT4-fs (mmcblk0p2): recovery complete
[ 2.919061] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. )
[ 2.927158] VFS: Mounted root (ext3 filesystem) on device 179:2.
[ 2.940699] devtmpfs: mounted
[ 2.945411] Freeing unused kernel memory: 1024K
[ 2.950074] Run /sbin/init as init process
[ 3.180430] systemd[1]: Failed to insert module 'ip_tables': Function not imd
[ 3.204288] systemd[1]: systemd 226 running in system mode. (+PAM -AUDIT -SE)
[ 3.222576] systemd[1]: Detected architecture arm.
Welcome to The �Ångstr�öm Distribution v2014.12!
[ 3.249729] systemd[1]: Set hostname to <arria10>.
[ 3.495229] systemd[1]: Configuration file /lib/systemd/system/altera-gsrd.s.
[ 3.532422] systemd[1]: Started Dispatch Password Requests to Console Direct.
[ OK ] Started Dispatch Password Requests to Console Directory Watch.
[ 3.569199] systemd[1]: Listening on networkd rtnetlink socket.
[ OK ] Listening on networkd rtnetlink socket.
[ 3.599032] systemd[1]: Listening on Syslog Socket.
[ OK ] Listening on Syslog Socket.
[ 3.628999] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
[ OK ] Listening on /dev/initctl Compatibility Named Pipe.
[ 3.669222] systemd[1]: Listening on udev Control Socket.
[ OK ] Listening on udev Control Socket.
[ 3.699150] systemd[1]: Created slice System Slice.
[ OK ] Created slice System Slice.
[ OK ] Created slice system-serial\x2dgetty.slice.
[ OK ] Created slice User and Session Slice.
[ OK ] Reached target Slices.
[ OK ] Started Forward Password Requests to Wall Directory Watch.
[ OK ] Reached target Paths.
[ OK ] Reached target Swap.
[ OK ] Listening on Journal Socket (/dev/log).
[ OK ] Listening on udev Kernel Socket.
[ OK ] Created slice system-getty.slice.
[ OK ] Listening on Journal Socket.
Starting Remount Root and Kernel File Systems...
[ 4.056981] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
Starting Setup Virtual Console...
Starting Journal Service...
Mounting Debug File System...
Starting Apply Kernel Variables...
[ OK ] Mounted Debug File System.
[ OK ] Started Remount Root and Kernel File Systems.
[ OK ] Started Setup Virtual Console.
[ OK ] Started Apply Kernel Variables.
[ OK ] Started Journal Service.
Starting udev Coldplug all Devices...
Starting Load/Save Random Seed...
Starting Flush Journal to Persistent Storage...
Starting Create Static Device Nodes in /dev...
[ OK ] Started Load/Save Random Seed.
[ OK ] Started Create Static Device Nodes in /dev.
[ 4.592774] systemd-journald[74]: Received request to flush runtime journal 1
Starting udev Kernel Device Manager...
[ OK ] Reached target Local File Systems (Pre).
Mounting /tmp...
[ OK ] Mounted /tmp.
[ OK ] Started udev Coldplug all Devices.
[ OK ] Reached target Local File Systems.
[ OK ] Started Flush Journal to Persistent Storage.
[ OK ] Started udev Kernel Device Manager.
Starting Create Volatile Files and Directories...
[ OK ] Started Create Volatile Files and Directories.
Starting Network Time Synchronization...
Starting Update UTMP about System Boot/Shutdown...
[ OK ] Started Update UTMP about System Boot/Shutdown.
[ OK ] Started Network Time Synchronization.
[ OK ] Reached target System Time Synchronized.
[ OK ] Reached target System Initialization.
[ OK ] Started Daily Cleanup of Temporary Directories.
[ OK ] Reached target Timers.
[ OK ] Listening on D-Bus System Message Bus Socket.
[ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
Starting sshd.socket.
[ OK ] Listening on RPCbind Server Activation Socket.
[ OK ] Found device /dev/ttyS0.
[ OK ] Listening on sshd.socket.
[ OK ] Reached target Sockets.
[ OK ] Reached target Basic System.
Starting Login Service...
[ OK ] Started Kernel Logging Service.
[ OK ] Started System Logging Service.
[ OK ] Started D-Bus System Message Bus.
Starting Network Service...
Starting Connection service...
Starting Altera GSRD initialization...
Starting Avahi mDNS/DNS-SD Stack...
[ OK ] Started Timestamping service.
[ OK ] Started Network Service.
[ OK ] Started Avahi mDNS/DNS-SD Stack.
[ OK ] Started Login Service.
[ OK ] Started Connection service.
[ OK ] Reached target Remote File Systems.
Starting Permit User Sessions...
[ OK ] Reached target Network.
Starting Lightning Fast Webserver With Light System Requirements...
Starting Network Name Resolution...
[ 9.223031] Micrel KSZ9031 Gigabit PHY stmmac-0:07: attached PHY driver [Mic)
[ 9.237338] dwmac1000: Master AXI performs any burst length
[ 9.242973] socfpga-dwmac ff800000.ethernet eth0: No Safety Features supportd
[ 9.250548] socfpga-dwmac ff800000.ethernet eth0: IEEE 1588-2008 Advanced Tid
[ OK ] Started Permit User Sessions.
[ OK ] Started Lightning Fast Webserver With Light System Requirements.
[ 9.328311] Si5345 successfully recognized!
[ 9.339262] Si5345 design id =
[ 9.343435] DEVICE REV = 0x03
[ 9.351280] I2C ADDR = 0x70
[ 9.355356] OOF and LOS Alarms = 0x11
[ 9.359441] Holdover and LOL Status = 0x2F
[ 9.363515] Internal Error Flags = 0x00
[ 9.367588] SI5345 free run
Starting WPA supplicant...
[ OK ] Started Serial Getty on ttyS0.
[ OK ] Started Getty on tty1.
[ OK ] Reached target Login Prompts.
[ 9.675951] socfpga-dwmac ff800000.ethernet eth0: Si5345 I2C supported
[ OK [ 9.687307] socfpga-dwmac ff800000.ethernet eth0: registered PTP clock
] Started WPA supplicant.
[ OK ] Started Network Name Resolution.
[ 12.809379] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - f
[ 12.817815] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
.---O---.
| | .-. o o
| | |-----.-----.-----.| | .----..-----.-----.
| | | __ | ---'| '--.| .-'| | |
| | | | | |--- || --'| | | ' | | | |
'---'---'--'--'--. |-----''----''--' '-----'-'-'-'
-' |
'---'
The Angstrom Distribution arria10 ttyS0
Angstrom v2014.12 - Kernel 5.2.0-rc3-g4b574d3-dirty
arria10 login: root (automatic login)
Last login: Thu Aug 29 22:29:07 UTC 2019 on ttyS0
mount /dev/mmcblk0p1 to ~/sdcard
[ 14.803367] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data.
eth0 Link encap:Ethernet HWaddr 4a:b9:ac:5a:05:66
inet addr:192.168.100.49 Bcast:192.168.100.255 Mask:255.255.255.0
inet6 addr: fe80::48b9:acff:fe5a:566/64 Scope:Link
UP BROADCAST RUNNING MULTICAST DYNAMIC MTU:1500 Metric:1
RX packets:1 errors:0 dropped:0 overruns:0 frame:0
TX packets:8 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:201 (201.0 B) TX bytes:1323 (1.2 KiB)
Interrupt:31 Base address:0xc000
```
# eth0 ethtool
```
oot@arria10:~/sdcard# ethtool -T eth0
Time stamping parameters for eth0:
Capabilities:
hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
PTP Hardware Clock: 0
Hardware Transmit Timestamp Modes:
off (HWTSTAMP_TX_OFF)
on (HWTSTAMP_TX_ON)
Hardware Receive Filter Modes:
none (HWTSTAMP_FILTER_NONE)
all (HWTSTAMP_FILTER_ALL)
ptpv1-l4-event (HWTSTAMP_FILTER_PTP_V1_L4_EVENT)
ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
```
# ptp sync
1. core 0 linux has ptp4l command
2. ptp sync by eth0
3. log is printed by core 0 - linuxptp4l
```
ptp4l[619.146]: master offset -576 s0 freq +21 path delay 7450
```
special case
1. meet RU crash when ptp sync fail
2. unknown
# core 1 start up (rrh_config_enable_core1)
Before enabling core1 , ptp need to be started firstly.
```
//*********************************************************************************
// Check if the the PTP4l is running or not
// Because there is an endian issue, the return value is located at higher byte.
// Hence, need extra right shifting to get exact retrun value from "system"
//*********************************************************************************
sprintf(buf, "existed=$(ps -d |grep ptp4l); if [ -z \"$existed\" ]; then echo -e \"Start PTP...\n\"; exit %d; else echo -e \"PTP is running\n\"; exit %d; fi",
RET_PTP_NOT_RUNNING, RET_PTP_IS_RUNNING);
check = system(buf) >> 8;
//printf("\n\nThe return value is %x v4\n\n", check);
if (check == RET_PTP_NOT_RUNNING)
system("/usr/linuxptp/ptp4l -i eth0 -smf /usr/linuxptp/configs/user_gen.cfg -l 4 &");
else if (check == RET_PTP_IS_RUNNING)
syscall(ENABLE_CORE1_SYSCALL);
```
so I started linuxp4p4l by manual command.
```
nohup /usr/linuxptp/ptp4l -i eth0 -smf /usr/linuxptp/configs/user_gen.cfg -l 4 > ptp.log 2>&1 &
```
then start ./init_rrh_config_enable_cuplane
```
root@arria10:~/test# ./init_rrh_config_enable_cuplane
37268dc0f781ed760ab748355154ae7ed47ccd21 master
9632b36b2f2bf56bccb42cf6ac2b24c4009e0ffe init_rrh_config_enable_cuplane
17de5b10c20751302295c7d9cbb54b696d302c87 bootimage_cuplane.bin
9e48fc03c6a9c4271cce87f7ffd2f86b60701ce8 ../sdcard/ghrd_10as066n2.core.rbf
e92b9d32cde7122fb389c5be8f9d96dbbdaf1053 RRU Interface SHA1 value
Start to write bootimage_cuplane.bin from 0x2e800000
File_size of bootimage_cuplane.bin 227344 words
Write bootimage_cuplane.bin done!
PTP is running[ 286.974616] Load cuplane on 0x2e800000
root@arria10:~/test# NULL ADRV9025 device pointer
RRH_state=0
RRU Interface SHA1 value
e92b9d32cde7122fb389c5be8f9d96dbbdaf1053
RRU Branch information
master
RRU Commit information
327095a7c3b9acf208d3995d3e6c1f6ac45f487c
ALT interrupt init!
INFO: Setting up global interrupts.
INFO: Setting up CPU interrupts.
INFO: Configuring buttons.
INFO: Enabling CPU interrupts.
INFO: Enabling global interrupts.
Interrupt init!
ad9025 init...
p_jesd204b_status = 0xf03
0 my_framerStatus.framerSyncNeCount 0x0
0 my_framerStatus.qbfStateStatus 0xd
0 my_framerStatus.status 0xa
0 my_framerStatus.syncNSel 0x0
0 my_deframerStatus.status 0x87
JESD rx_err0 = 00000004
JESD rx_err1 = 00000000
JESD rx_status0 = 00000039
JESD rx_status1 = 00000000
JESD rx_status2 = 000f0000
JESD rx_status3 = 0000000f
JESD rx_status4 = 000000aa
JESD rx_status5 = 000000aa
JESD rx_status6 = 00000000
JESD rx_status7 = 000f000f
JESD ilas_data1 = 071f0383
JESD ilas_data2 = 00202f0f
jesd204M fpga 8 ad9025 8
jesd204K fpga 32 ad9025 32
jesd204F fpga 4 ad9025 4
JESD Link NP fpga 16 ad9025 16
JESD dll_ctrl = 00000001
JESD ilas_octet0 = 83000001
JESD ilas_octet1 = 0f071f03
JESD ilas_octet2 = 0000202f
JESD ilas_octet3 = 00004e00
JESD rx_test = 00000000
txLinkSel 0x1 adrv9025LinkStatus 0x1
rxLinkSel 0x1 fpga9025LinkStatus 0x1
ad9025 bring up completed!
Before: RxEn=00000000 TxEn=00000000
After: RxEn=00000000 TxEn=0000000f
ad9025 tx on!
ad9025 tx on!
new LO=3750000 rtn_LO1=3750000 rtn_LO2=0
Before: RxEn=00000000 TxEn=0000000f
After: RxEn=00000000 TxEn=0000000f
ad9025 tx on!
Current Tx control mode = SPI_mode
Current Rx control mode = SPI_mode
Current ORx control mode = SPI_mode
PA=0000000f TxEn=00000000 TRSwitch=00000000Initial Tx/Rx attenuation: [0]=14/0 [1]=14B
xRAN Initial...num_trx_en = 00000004, dl_type1_port_id = 00003210, dl_type3_0_port_id0
xRAN Initial...
Enable 10GBE...96fff000
10GBE RxMTU=9000 TxMTU=9000 status=d6fff000
addr:FF201000 value:D6FFF000
xran 10GBE is not ready... d6fff000
AP_PORT_EN=0fread-back mailbox configuration=00000100
read-back=00007fff i[01]=0000 q[01]=0000
read-back=00007fff i[02]=0000 q[02]=0000
read-back=00007fff i[03]=0000 q[03]=0000
read-back=00007fff i[04]=0000 q[04]=0000
read-back=00007fff i[05]=0000 q[05]=0000
read-back=00007fff i[06]=0000 q[06]=0000
read-back=00007fff i[07]=0000 q[07]=0000
read-back=00007fff i[08]=0000 q[08]=0000
read-back=00007fff i[09]=0000 q[09]=0000
read-back=00007fff i[10]=0000 q[10]=0000
read-back=00007fff i[11]=0000 q[11]=0000
read-back=00007fff i[12]=0000 q[12]=0000
read-back=00007fff i[13]=0000 q[13]=0000
read-back=00007fff i[14]=0000 q[14]=0000
read-back=00007fff i[15]=0000 q[15]=0000
read-back=00007fff i[16]=0000 q[16]=0000
read-back=00007fff i[17]=0000 q[17]=0000
read-back=00007fff i[18]=0000 q[18]=0000
read-back=00007fff i[19]=0000 q[19]=0000
read-back=00007fff i[20]=0000 q[20]=0000
read-back=00007fff i[21]=0000 q[21]=0000
read-back=00007fff i[22]=0000 q[22]=0000
read-back=00007fff i[23]=0000 q[23]=0000
read-back=00007fff i[24]=0000 q[24]=0000
read-back=00007fff i[25]=0000 q[25]=0000
read-back=00007fff i[26]=0000 q[26]=0000
read-back=00007fff i[27]=0000 q[27]=0000
In tcu_init: reset tcu
```
# The ptp4l has been modified.
source : rrh-linux-master-09f118c66426bc16a3d017c65d912f022b2ba399\app\linuxptp
# user-servo.c
```
/*
* File: user_servo.c
* Created on: 2019/11/04
* Author: Kurt Li
*
*/
/* standard library */
#include <stdint.h>
#include <stdlib.h>
#include <math.h>
#include <sys/syscall.h>
#include <sys/mman.h>
#include <unistd.h>
#include "config.h"
#include "print.h"
#include "servo_private.h"
#include "user_servo.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <unistd.h>
uint8_t share_lock_status = 0;
struct user_servo
{
struct servo servo;
int64_t offset[2];
uint64_t local[2];
double drift;
double last_freq;
int count;
};
static double user_servo_sample(struct servo *servo,
int64_t offset,
uint64_t local_ts,
double weight,
enum servo_state *state)
{
struct user_servo *s = container_of(servo, struct user_servo, servo);
static int64_t ptpv2_servo_t1_a;
static int64_t ptpv2_servo_t2_a;
static uint8_t pdv_valid_counter;
static uint8_t tuning_interval;
static uint8_t check_counter;
static uint32_t localdiff;
int64_t curr_path_delay;
int64_t pdv_delay;
double ratio;
double freq = s->last_freq;
uint8_t status;
unsigned int share_mem_addr = 0;
int *map = NULL;
int _fdmem;
const char memDevice[] = "/dev/mem";
static uint8_t check_lock_counter = 0;
switch(s->count)
{
case US_INIT:
pr_debug("US_INIT");
tuning_interval = 10;
pdv_valid_counter = 0;
check_counter = 0;
localdiff = 0;
ptpv2_servo_t1_a = tmv_to_nanoseconds(servo->tsp->t1);
ptpv2_servo_t2_a = tmv_to_nanoseconds(servo->tsp->t2);
*state = SERVO_UNLOCKED;
s->count = US_TUNING_FREQ_COARSE;
break;
case US_TUNING_FREQ_COARSE:
pr_debug("US_TUNING_FREQ_COARSE");
#if 0
localdiff = (tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a)/1e9;
pr_debug("localdiff/freq_est_interval %lld/%d",
localdiff, tuning_interval);
#endif
localdiff++;
pr_debug("localdiff/freq_est_interval %d/%d",
localdiff, tuning_interval);
ratio = (double)(tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a) /
(double)(tmv_to_nanoseconds(servo->tsp->t2)-ptpv2_servo_t2_a);
freq = (1.0 - ratio) * 1e9;
pr_debug("t5-t1 %lld ", tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a);
pr_debug("t6-t2 %lld ", tmv_to_nanoseconds(servo->tsp->t2)-ptpv2_servo_t2_a);
pr_debug("ratio %+7.0f ", ratio);
pr_debug("freq %+7.0f ", freq);
if(localdiff<tuning_interval)
{
*state = SERVO_UNLOCKED;
}
else
{
*state = SERVO_LOCKED;
if(abs(freq)<45)
{
if(check_counter>2)
{
*state = SERVO_JUMP;
s->count = US_CHECK_PDV;
check_counter = 0;
}
else
{
check_counter++;
}
}
else
{
check_counter = 0;
}
pr_debug("check_counter %d", check_counter);
if(freq!=0)
{
ptpv2_servo_t1_a = tmv_to_nanoseconds(servo->tsp->t1);
ptpv2_servo_t2_a = tmv_to_nanoseconds(servo->tsp->t2);
localdiff = CLEAR;
}
}
break;
case US_CHECK_PDV:
pr_debug("US_CHECK_PDV");
/* Path Delay = ((T2-T1)+(T4-T3))/2 */
curr_path_delay = (tmv_to_nanoseconds(servo->tsp->t2)-
tmv_to_nanoseconds(servo->tsp->t1)+
tmv_to_nanoseconds(servo->tsp->t4)-
tmv_to_nanoseconds(servo->tsp->t3))>>1;
pdv_delay = curr_path_delay-
tmv_to_nanoseconds(servo->tsp->filtered_delay);
if(abs(pdv_delay)<40)
{
pdv_valid_counter++;
if(pdv_valid_counter>7)
{
tuning_interval = 4;
}
else
{
tuning_interval = 10;
}
if(check_counter>10)
{
if(abs(offset)<100)
{
(tuning_interval<10)?pr_debug("high-sensitivity\n"):pr_debug("low-sensitivity\n");
s->count = US_TUNING_FREQ_FINE;
check_counter = 0;
}
else
{
*state = SERVO_JUMP;
}
}
}
check_counter++;
ptpv2_servo_t1_a = tmv_to_nanoseconds(servo->tsp->t1);
ptpv2_servo_t2_a = tmv_to_nanoseconds(servo->tsp->t2);
break;
case US_TUNING_FREQ_FINE:
pr_debug("US_TUNING_FREQ_FINE");
#if 0
localdiff = (tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a)/1e9;
pr_debug("localdiff/freq_est_interval %lld/%d",
localdiff, tuning_interval);
#endif
localdiff++;
pr_debug("localdiff/freq_est_interval %d/%d",
localdiff, tuning_interval);
ratio = (double)(tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a) /
(double)(tmv_to_nanoseconds(servo->tsp->t2)-ptpv2_servo_t2_a);
freq = (1.0 - ratio) * 1e9;
pr_debug("t5-t1 %lld ", tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a);
pr_debug("t6-t2 %lld ", tmv_to_nanoseconds(servo->tsp->t2)-ptpv2_servo_t2_a);
pr_debug("ratio %+7.0f ", ratio);
pr_debug("freq %+7.0f ", freq);
if(localdiff<tuning_interval)
{
*state = SERVO_UNLOCKED;
}
else
{
*state = SERVO_LOCKED;
if(abs(freq)<40)
{
if(check_counter>3)
{
s->count = US_TRACKING_PPS;
check_counter = 0;
}
else
{
check_counter++;
}
}
else
{
check_counter = 0;
}
pr_debug("check_counter %d", check_counter);
if(abs(freq)!=0)
{
ptpv2_servo_t1_a = tmv_to_nanoseconds(servo->tsp->t1);
ptpv2_servo_t2_a = tmv_to_nanoseconds(servo->tsp->t2);
localdiff = CLEAR;
}
}
break;
case US_TRACKING_PPS:
pr_debug("US_TRACKING_PPS");
offset = tmv_to_nanoseconds(servo->tsp->t2)-
tmv_to_nanoseconds(servo->tsp->t1)-
tmv_to_nanoseconds(servo->tsp->filtered_delay);
#if 0
localdiff = (tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a)/1e9;
pr_debug("localdiff/freq_est_interval %lld/%d",
localdiff, tuning_interval);
#endif
localdiff++;
pr_debug("localdiff/freq_est_interval %d/%d",
localdiff, tuning_interval);
ratio = (double)(tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a) /
(double)(tmv_to_nanoseconds(servo->tsp->t2)-ptpv2_servo_t2_a);
freq = (1.0 - ratio) * 1e9;
pr_debug("t5-t1 %lld ", tmv_to_nanoseconds(servo->tsp->t1)-ptpv2_servo_t1_a);
pr_debug("t6-t2 %lld ", tmv_to_nanoseconds(servo->tsp->t2)-ptpv2_servo_t2_a);
pr_debug("ratio %+7.0f ", ratio);
pr_debug("offset %lld ", offset);
pr_debug("freq %+7.0f ", freq);
if(localdiff<tuning_interval)
{
*state = SERVO_UNLOCKED;
}
else
{
if ((servo->first_update &&
servo->first_step_threshold &&
servo->first_step_threshold < llabs(offset)) ||
(servo->step_threshold &&
servo->step_threshold < llabs(offset)))
{
s->count = US_INIT;
}
else
{
*state = SERVO_LOCKED;
freq += (double)(offset/tuning_interval);
pr_debug("final freq %+7.0f ", freq);
if (freq < -servo->max_frequency)
{
freq = -servo->max_frequency;
}
else if (freq > servo->max_frequency)
{
freq = servo->max_frequency;
}
else
{
/* Do nothing */
}
}
if(abs(freq)<40&&abs(offset)<40)
{
check_counter++;
if(check_counter>10)
{
check_counter = 11;
share_lock_status = 1;
pr_info("LOCKED!");
if(check_lock_counter==6)
{
syscall(500);
check_lock_counter = 10;
}
else if(check_lock_counter<6)
{
check_lock_counter++;
}
}
}
else
{
pr_info("TRACKING...");
share_lock_status = 0;
check_counter = 0;
}
pr_debug("check_counter %d/10", check_counter);
ptpv2_servo_t1_a = tmv_to_nanoseconds(servo->tsp->t1);
ptpv2_servo_t2_a = tmv_to_nanoseconds(servo->tsp->t2);
localdiff = CLEAR;
}
break;
}
_fdmem = open(memDevice, O_RDWR | O_SYNC);
if(_fdmem < 0)
{
pr_err("Fail to open the /dev/mem !\n");
return 0;
}
map = (int *)(mmap(0,20,PROT_READ | PROT_WRITE,MAP_SHARED,_fdmem, 0xFFE38000));
*((volatile unsigned int *)(map)) = share_lock_status;
munmap(map, 20);
pr_debug("share_lock_status %d", share_lock_status);
close(_fdmem);
asm volatile("" ::: "memory");
s->last_freq = freq;
return freq;
}
```
code in core1 text_xran
```
status = 0xFF;
while(1){
#if !defined(DUAL_ARM_CORE)
cltr_z_reset_check();
#else
/* In dual core image, check if core1 is needed to be reset. */
core1_reset_check();
rrh_check_logger_ptr();
#endif
#if defined(ONE_PPS_TICK_LOG)
if (g_1pps_wr_idx > 2)
{
printf("%d %d\n", g_1pps_wr_idx-1, g_1pps_tick_time_log[g_1pps_wr_idx-1] - g_1pps_tick_time_log[g_1pps_wr_idx-2]);
}
#endif
#if (defined(RRH_S1) || defined(RRH_MADURA)) && !defined(PTPV2_EN) && !defined(__FIFO_EMPTY_DETECT__)
//set_and_check_phase_shift(100);
#endif
check_dpd_hotkey(g_xran_params.rf_en_bit_mask);
log_sw_tick_print();
xran_dl_log_print(g_seconds, g_sw_irq_idx);
#if (defined(RRH_S1) || defined(RRH_MADURA)) && defined(PTPV2_EN)
#if !defined(DUAL_ARM_CORE)
/* Send PTP packets out if needed */
net_loop_tx_ptpv2_task();
/* check the ethernet for a new packet */
if (eth_dev) eth_dev->recv(eth_dev);
/* Received PTP packets if incoming packet exists */
net_loop_rx_ptpv2_task();
/* Check for a timeout, and run the timeout handler if we have one. */
net_check_timeout();
#endif
/* When PTP is locked, start SW tick counting up.
However, when PTP is out of lock again, counting up of SW tick is not stopped */
if (ptpv2_read_lock_status())
{
uint32_t new_1pps_time = RRH_READ_WORD(REG_TCU_LOG_EMAC_1PPS_NEG); //RRH_READ_WORD(0xFF201B8C); //negative edge time of 1pps
/* There is constant offset in our PPS signal and GPS PPS signal. Hence, use
the following calculation to compensate this diff */
if (new_1pps_time < PPS_CONST_OFFSET)
{
new_1pps_time += (0xFFFFFFFF - PPS_CONST_OFFSET + 1);
}
else
{
new_1pps_time -= PPS_CONST_OFFSET;
}
if (g_curr_1pps_time == 0)
{
/* Update TCU time @ negative edge of 1PPS.
* Do not start SW tick counting when PTP is just locked.
* Use 1PPS signal only after PTP is locked */
g_curr_1pps_time = new_1pps_time;
#if !defined(INTEL_RELEASE)
printf("Latch 1st 1pps time=%08x\n", g_curr_1pps_time);
#endif
}
else if ((g_en_sw_irq_cnt == 0) && (g_curr_1pps_time != new_1pps_time))
{
uint32_t top_diff = 0xFFFFFFFF - g_curr_1pps_time;
uint32_t diff_two = (new_1pps_time < g_curr_1pps_time)? (top_diff + 1 + new_1pps_time): (new_1pps_time - g_curr_1pps_time);
/* If time difference between two successive 1pps is not 122880000 and current 1pps will be wrapped after 50 Ticks, wait next */
if (!((top_diff > TCU_INTERVAL_HALF_SLOT*50) && (diff_two == 122880000)))
{
#if !defined(INTEL_RELEASE)
printf("Latch 2nd 1pps time=%08x curr=%08x diff=%d\n", g_curr_1pps_time, new_1pps_time, diff_two);
#endif
g_curr_1pps_time = new_1pps_time;
}
else
{
#if !defined(INTEL_RELEASE)
printf("Latch 2nd 1pps time=%08x curr=%08x\n", g_curr_1pps_time, new_1pps_time);
#endif
g_prv_1pps_time = new_1pps_time;
g_curr_1pps_time = new_1pps_time;
g_en_sw_irq_cnt = 1;
}
}
else if ((g_en_sw_irq_cnt == 1) && (g_en_1pps_tick_log == 1))
{
#if !defined(INTEL_RELEASE)
uint32_t hps_sec = RRH_READ_WORD(REG_HPS_SEC_TIMER);
rrh_status_update(&g_xran_params, RRH_READY_FOR_DATA);
printf("Align: %d %d %d %d\n", g_sw_tick_time_log[0], g_sw_tick_time_log[1], g_sw_tick_time_log[2], g_sw_tick_time_log[3]);
printf("%s%s%s", g_str_eth_statistic[0], g_str_eth_statistic[1], g_str_eth_statistic[2]);
#if !defined(RRH_MADURA)
#else
char *pa_onoff = ((RRH_READ_WORD(REG_RF_CTRL_PA_ON_ADDR) & 0x0F)>0)?"PA_ON":"PA_OFF";
char *ctrl_mode = ((RRH_READ_WORD(REG_RF_CTRL_PA_LNA_SOURCE_ADDR)>0))?"":"TDD";
printf("Latch later 1pps time=%08x swi4010=%08x xran_sec=%08x acc_diff[%d]=%d hps_sec=%d cur_sec=%d %s %s\n",
g_curr_1pps_time, g_swi4010_time, g_xran_sec_time, g_curr_1pps_idx, g_1pps_time[g_curr_1pps_idx], hps_sec, g_seconds, pa_onoff, ctrl_mode);
if (hps_sec & 0x03 == 3)
{
#if !defined(EN_DPD)
dbfs_check(0, 0, g_xran_params.rf_en_bit_mask);
#else
ad9025_dpd_status_get(g_xran_params.rf_en_bit_mask);
#endif
}
#endif //#if !defined(RRH_MADURA)
#else //#if !defined(INTEL_RELEASE)
printf("%08x %08x %08x [%d]=%d\n", g_curr_1pps_time, g_swi4010_time, g_curr_1pps_idx, g_curr_1pps_idx, g_1pps_time[g_curr_1pps_idx]);
#endif
g_en_1pps_tick_log = 0;
}
}
#if defined(DUAL_ARM_CORE)
else //if (ptpv2_read_lock_status())
{
/* When RRH is in RRH_READY_FOR_DATA but out-of-lock some time after,
* the state of RRH must be updated to RRH_FAILED to let core0 to reset core 1 */
if (g_en_sw_irq_cnt == 1)
{
rrh_status_update(&g_xran_params, RRH_FAILED);
}
}
#endif
#endif //#if (defined(RRH_S1) || defined(RRH_MADURA)) && defined(PTPV2_EN)
```
## RU boot enable core 1
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