### Decoder
#### Spec.
1. Input : opcode
2. output : RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUop

#### Instruction Set
- R-type : add, sub, AND, OR, NOR, slt
- I-type : lw, sw, beq, bne, addi

#### 2-bits control signals
1. ALUop

| ALUop | Opration | Instruction |
| ----- | -------- | -------- |
| 00 | add | lw/sw, addi |
| 01 | sub | beq, bne |
| 10 | Depand on Func. | R-type |
| 11 | Preserve | Preserve |

2. Branch

| Branch_o | Instruction |
| -------- | --- |
| `00` | Non-branch |
| `01` | beq |
| `10` | bne |
| `11` | Preserve |

#### Control Signal in each stage

| IF | ID | EX | MEM | WB |
| ---- | ---- | ---- | --- | --- |
| X | X | ALUop(2)<br>ALUSrc(1)<br>RegDst(1) | Branch(2)<br>MemWrite(1)<br>MemRead(1) | MemtoReg(1)<br>RegWrite(1) |

### Hardware
This circuit can't execute `bne`
### Pipeline Register
Number of bits in each pipeline register

- IF/ID : 64-bits
- ID/EX : 148-bits
- EX/MEM : 108-bits
- MEM/WB : 51-bits