---
# System prepended metadata

title: What is an example of fixing a bug in a core?
tags: [FPGA]

---

Here are a few concrete examples of “fixing a bug in a core” (an [FPGA](https://www.ampheo.com/c/fpgas-field-programmable-gate-array) IP core, a CPU core, or a soft-core). I’ll use FPGA-style “core” examples since that’s the most common meaning in this context.

![2020_16_04_fpga_hgi_rub_02](https://hackmd.io/_uploads/H1R-qU6f-e.jpg)

**Example 1: AXI-Stream FFT core bug — TLAST handled incorrectly**

**Symptom:** Every few frames the FFT output is shifted/scrambled, and an error flag like event_tlast_unexpected fires.

**Root cause (typical):**

* The core treats TLAST as “end of frame” even when TREADY=0.
* So if the upstream asserts TLAST while the core is backpressuring, the core may “see” end-of-frame at the wrong cycle.

**Fix:**

* Only latch/act on TLAST when a valid transfer happens:
  * transfer = TVALID && TREADY
  * frame_end <= transfer && TLAST
* Reset internal sample counter only on frame_end.

**Regression test:**

* Randomly toggle TREADY (backpressure) while sending frames.
* Check that output frame length stays exactly N samples and TLAST appears exactly once at the end.

**Example 2: UART core bug — receive overruns at high baud**

**Symptom:** At 921600 baud, bytes occasionally drop or repeat.

**Root cause (typical):**

RX sampling point is off by ~½ bit (bad baud divider rounding), or the core only has a 1-byte buffer so any short CPU stall causes overrun.

**Fix:**

* Use a fractional baud generator or correct rounding for the divider.
* Add a small FIFO (e.g., 16 bytes) on RX and assert an overrun flag when FIFO is full.

**Regression test:**

Loopback test with known PRBS pattern for millions of bytes; check CRC = OK and no overrun flags.

**Example 3: Cache/CPU core bug — missing pipeline stall on load-use hazard**

**Symptom:** A program fails only with certain instruction sequences, especially LOAD r1, [addr]; ADD r2, r1, r3 immediately after.

**Root cause (typical):**

The core doesn’t stall or forward the loaded value soon enough, so the ADD reads the old r1.

**Fix:**

Add hazard detection: if an instruction uses a register that is the destination of a load in the previous stage, insert a bubble/stall or implement forwarding from the memory stage.

**Regression test:**

Run a directed test that stresses all hazard patterns + random instruction tests.

**What “fixing a bug” usually includes (quick checklist)**

* Reproduce with a minimal test case
* Identify the failing condition (timing, handshake, overflow, hazard)
* Patch RTL/microcode/firmware
* Add a regression test so it never returns
* Re-run synthesis/STA (for [FPGA](https://www.ampheoelec.de/c/fpgas-field-programmable-gate-array)) or full verification (for CPU core)