###### tags: `CERN`
# Analog Devices ADC
[toc]

# Descriptions

## Evaluation Board

[Board is AD9695-1300EBZ / AD9695-625EBZ evaluation board](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9695.html#eb-overview )

The AD9695-1300EBZ / AD9695-625EBZ supports the AD9695, a 14-bit, 1300MSPS / 625MSPS dual analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support direct RF sampling analog signals of up to 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.

The AD9695-1300EBZ can be used to evaluate the AD9697 as the performance is identical except for power consumption.

**Features and Benefits**
* Full featured evaluation board for the AD9695-1300 / AD9695-625.
* JESD204B coded serial digital outputs with support for lane rates up to 16Gbps/lane.
* Wide full power bandwidth supports IF sampling of signals up to 2GHz.
* Four Integrated wide-band decimation filter and NCO blocks supporting multi-band receivers.
* Flexible SPI interface controls various product features and functions to meet specific system requirements.
* Programmable fast over range detection and signal monitoring.

## Chip

[Chip is AD9695, a 14-bit, 1300 MSPS/625 MSPS, JESD204B dual analog-to-digital converter (ADC)](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9695.html#eb-overview)

The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support direct RF sampling analog signals of up to 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.

The AD9695-1300EBZ can be used to evaluate the AD9697 as the performance is identical except for power consumption.

−40°C to +105°C junction temperature range.

**Features and Benefits**
* JESD204B (Subclass 1) coded serial digital outputs
* Lane rates up to 16 Gbps
* 1.6 W total power at 1300 MSPS
* 800 mW per ADC channel
* SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range)
* SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range)
* Noise density
* −153.9 dBFS/Hz (1.59 VP-P input range)
* −155.6 dBFS/Hz (2.04 VP-P input range)
* 0.95 V, 1.8 V, and 2.5 V supply operation
* No missing codes
* Internal ADC voltage reference
* Flexible input range
* 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical)
* 2 GHz usable analog input full power bandwidth
* \>95 dB channel isolation/crosstalk
* Amplitude detect bits for efficient AGC implementation
* 2 integrated digital downconverters per ADC channel
* 48-bit NCO
* Programmable decimation rates
* Differential clock input
* SPI control
* Integer clock divide by 2 and divide by 4
* Flexible JESD204B lane configurations
* On-chip dithering to improve small signal linearity

## Multichannel System Clocking Device
**clock distribution and multichannel synchronization**

[The AD-SYNCHRONA14-EBZ is an ideal self-contained device](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ad-synchrona14-ebz.html#eb-overview) to use in evaluation and prototyping of applications that need a highly accurate frequency and phase-controlled source clock. It is designed around the Analog Devices AD9545 and HMC7044 and greatly simplifies clock distribution and multi-channel synchronization in complex systems. It is intended to be used by trained professionals in a laboratory environment, and not intended as an end product for commercial use. It can be taken as a complete reference design and customised as required for any end customer applications. Full design details are made available free of charge.

The AD-SYNCHRONA14-EBZ comes in a 1U mechanical form factor. Using popular industry connector SMA and TwinAX interfaces most labs will already have the needed cables.

With its internal OCXO it can operate in standalone mode or be fed from a choice of external sources, such as 3 separate high speed differential clock inputs, a 10MHz reference and 1PPS. This flexibility combined with the capability to select either of the internal VCXO options of 100MHz or 122.88MHz, gives almost unlimited choice for the frequency of interest and accuracy needed for a wide variety of application areas.

APPLICATIONS

* High accuracy reference clock distribution
* Systems clocked from a single source
* Clocks derived from 100MHz or 122.88MHz
* Phased Array Systems, RADAR, EW, SATCOMS, SDR
* Bench Equipment
* Remote controlled operation

**Features and Benefits**

* Processing System
* Raspberry Pi 4, ARM Cortex-A72, 2GB SDRAM
* User Interfaces
* Gigabit Ethernet
* 2 × USB 3.0 ports
* 2 × USB 2.0 ports
* SPI interface
* GPIO
* 2 bicolor LEDs
* Male pin header
* Clock Processing Devices
* HMC7044 (High Performance, 3.2 GHz, 14-Output Jitter Attenuator)
* AD9545 (1 PPS Synchronizer and Adaptive Clock Translator)
* Clock Outputs
* 4 x TWINAX LVPECL AC&DC coupled, 100Ω diff
* 2 x SMA LVPECL AC coupled (Configurable differential outputs, 50Ω diff)
* 4 x SMA CMOS (Configurable differential outputs, 50Ω diff)
* 4 x SMA LVDS AC coupled (Configurable differential outputs, 50Ω diff)
* Clock Inputs
* 3 differential 100Ω SMA clock inputs
* PPS input
* SYNC input
* 10MHz input
* Internal references
* 100Mhz and 122.88Mhz Ultra-Low Phase Noise VCXO's (-165dBc/Hz)
* 40Mhz and 38.4Mhz TCXO's (±1ppm) 50MHz OCXO(+/- 10ppb)
* Internal references are software configurable
* Power supply
* DC 12V, 3A barrel jack

# Documents

## Evaluation Board

| Name | Site |
| -------- | -------- |
| AD9695-1300EBZ Board Product Page | https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9695.html |
| AD9695-1300EBZ Board Reference Design with ZCU | https://wiki.analog.com/resources/eval/user-guides/ad9695_fmc?force_rev=1 |
| AD9695-1300EBZ Board Files (schematic, component list etc.) | https://wiki.analog.com/_media/resources/eval/ad9695_evaluation_board_files.zip |

## Chip

| Name | Site |
| -------- | -------- |
| AD9695 Chip Product Page | https://www.analog.com/en/products/ad9695.html |
| AD9695 Chip Data Sheet | https://www.analog.com/media/en/technical-documentation/data-sheets/ad9695.pdf |

## Multichannel System Clocking Device

| Name | Site |
| -------- | -------- |
| AD-SYNCHRONA14-EBZ Product Page | https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ad-synchrona14-ebz.html#eb-overview |
| AD-SYNCHRONA14-EBZ User Guide | https://wiki.analog.com/resources/eval/user-guides/ad-synchrona14-ebz |

# Usage

## JESD204B

4 diffrential pin (SERDOUT) Data output


* JESD204B serial related

The ADC data outputs are internally connected to four **digital downconverters (DDCs)** through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator **(numerically controlled oscillator (NCO)**), and decimation filters. The NCO has the option to select up to 16 preset bands over the **general-purpose input/ output (GPIO) pins**, or use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9695 between the DDC modes is selectable via **SPI-programmable profiles.**

The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either **one lane, two lanes, or four lanes**, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the **SYSREF± and SYNCINB± input pins.**


The JESD204B link is described according to the following parameters:
* L is the number of lanes/converter device (lanes/link) (AD9695 value = 1, 2, or 4)
* M is the number of converters/converter device (virtual converters/link) (AD9695 value = 1, 2, 4, or 8)
* F is the octets/frame (AD9695 value = 1, 2, 4, 8, or 16)
* N' is the number of bits per sample (JESD204B word size) (AD9695 value = 8 or 16)
* N is the converter resolution (AD9695 value = 7 to 16)
* CS is the number of control bits/sample (AD9695 value = 0, 1, 2, or 3)
* K is the number of frames per multiframe (AD9695 value = 4, 8, 12, 16, 20, 24, 28, or 32 )
* S is the samples transmitted/single converter/frame cycle (AD9695 value = set automatically based on L, M, F, and N')
* HD is the high density mode (AD9695 = set automatically based on L, M, F, and N')
* CF is the number of control words/frame clock cycle/converter device (AD9695 value = 0)

Figure below shows a simplified block diagram of the AD9695 JESD204B link. By default, the AD9695 is configured to use two converters and four lanes. Converter A data is output to SERDOUT0± and/or SERDOUT1±, and Converter B is output to SERDOUT2± and/or SERDOUT3±. The AD9695 allows other configurations, such as combining the outputs of both converters onto a single lane, or changing the mapping of the A and B digital output paths. These modes are customizable, and can be set up via the SPI.


By default in the AD9695, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, or fast detect output.

The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self-synchronizing, polynomial-based algorithm defined by the equation 1 + x 14 + x 15 . The descrambler in the receiver is a self synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8-bit/10-bit encoder. The 8-bit/10-bit encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure below shows how the 14-bit data is taken from the ADC, how the tail bits are added, how the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure below shows the default data format.


The processing can be divided into layers that are derived from the open source initiative (OSI) model, widely used to describe the abstraction layers of communications systems. These layers are the transport layer, data link layer, and physical layer (serializer and output driver).

* **Transport Layer**
The transport layer handles packing the data (consisting of samples and optional control bits) into JESD204B frames that are mapped to 8-bit octets.

The packing of samples into frames are determined by the JESD204B configuration parameters for
number of lanes (L), number of converters (M), the number of octets per lane per frame (F), the number of samples per converter per frame (S), and the number of bits in a nibble group (sometimes called the JESD204 word size − N’).

Samples are mapped in order starting from Converter 0, then Converter 1, and so on until Converter M − 1. If S > 1, each sample from the converter is mapped before mapping the samples from the next converter. Each sample is mapped into words formed by appending converter control bits, if enabled,
to the LSBs of each sample. The words are then padded with tail bits, if necessary, to form nibble groups (NGs) of the appropriate size as determined by the N’ parameter. The following equation
can be used to determine the number of tail bits within a nibble group (JESD204B word): T = N' − N − CS

* **Data Link Layer**

The data link layer is responsible for the low level functions of passing data across the link. These include optionally scrambling the data, inserting control characters during the
initial lane alignment sequence (ILAS) and for frame and multiframe synchronization monitoring, and encoding 8-bit octets into 10-bit symbols.

* **Physical Layer**

The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data.


## Evaluation Board

### Signals to chip from PCB
| Name | Description | Signal |
| -------- | -------- | -------- |
| (P201/+, P203/-) P202 | ADC Sample Clock, ENCODE/CLOCK INPUT (CLK +/-) | Analog input, provide a clean, low jitter 1300 MHz clock (preferably via a shielded RG-58 50 Ω coaxial cable) and set the amplitude to 10 dBm |
| (J100/P,J102/N) or J101 | Input A (VI A_P/N)| Analog input ADC A |
| (J103/P,J105/N) or J104 | Input B (VI B_P/N)| Analog input ADC B|
| J200 | EXTERNAL SYSREF TO DUT (D_SYSREF_P/N SYSREF+/-)| Digital input, Active High JESD204B LVDS System Reference Input |
| VREF | TP100 | Reference Voltage Input (0.50 V)/Do Not Connect. This pin is configurable through the SPI as a no connect pin or as an input. Do not connect this pin if using the internal reference. This pin requires a 0.50 V reference voltage input if using an external voltage reference source. |

### Signals to fpga from PCB

| Name | Description | FMC PIN |
| -------- | -------- | -------- |
| J202 | EXTERNAL FPGA REFCLK (EXT_REFCLK_TO_FPGA+/- ) | TO FMC D4/D5 GBTCLK0_M2C_P/GBTCLK0_M2C_N |

### Signals fpga <=> chip

TO FPGA:

| Name | Description | FMC PIN |
| -------- | -------- | -------- |
| SERDOUT0 +/- |Data output, JESD204B serial out Lane 0 | A10/ A11 DP3_M2C_P/DP3_M2C_N|
| SERDOUT1 +/- |Data output, JESD204B serial out Lane 1 | A6/A7 DP2_M2C_P/DP2_M2C_N|
| SERDOUT2 +/- |Data output, JESD204B serial out Lane 2 | C6/C7 DP0_M2C_P/DP0_M2C_N |
| SERDOUT3 +/- |Data output, JESD204B serial out Lane 3 | A2/A3 DP1_M2C_P/DP1_M2C_N|

FROM FPGA:

**Code Group Synchronization (CGS)**

CGS is the process by which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K/ characters (/K28.5/ symbols). The receiver must locate the /K/ characters in its input data stream using clock and data recovery (CDR) techniques.

The receiver issues a synchronization request by asserting the SYNCINB± pin of the AD9695 low. The JESD204B Tx then begins sending /K/ characters. Once the receiver has synchronized, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINB±. The AD9695 then transmits an ILAS on the following local multiframe clock (LMFC) boundary.

| Name | Description | FMC PIN |
| -------- | -------- | -------- |
| SYNCINB +/- | Digital input , Active Low JESD204B LVDS/CMOS Sync Input | H10/H11 (TP200/TP201) LA04_P/LA04_N|

* SPI AND CONTROL REGISTERS

There is a voltage translator in between

| Name | Description | FMC PIN |
| -------- | -------- | -------- |
| SDIO_DUT | Digital control input/output, SDI_FROM_FPGA / SDO_TO_FPGA , SPI Serial Data Input/Output.| D9/H7 LA01_N_CC/LA02_P|
| SCLK_DUT |Digital control input, SCLK_FROM_FPGA , SPI Serial Clock.| D8 LA01_P_CC |
| CSB_DUT| Digital control input, CSB_FPGA_TO_DUT , SPI Chip Select (Active Low).| C10 LA06_P|


* GPIO MUX
There is a voltage translator in between

AD9695 has several functions that simplify the **automatic gain control (AGC)** function in a
communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the **fast detect control bits in Register 0x0245** of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

The AD9695 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a **3-wire serial port interface (SPI)** and or **PDWN/STBY** pin.

| Name | Description | FMC PIN |
| -------- | -------- | -------- |
| FDB_TO_BUF | FDB_TO_FPGA, Fast Detect Output for Channel B (FD_B). GPIO Pin B0 (GPIO_B0). | G10 LA03_N|
| FDA_TO_BUF | FDA_TO_FPGA, Fast Detect Output for Channel A (FD_A). General-purpose input/output (GPIO) Pin A0 (GPIO_A0). | G9 LA03_P|
| PWDN_TO_BUF | PWDN_TO_FPGA , Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby.| H8 LA02_N|

## Chip

## Multichannel System Clocking Device

# Example design

## ZCU

* Download necessary files (didnt work for this project, It assumes mezannine FMC is AD-FMCOMMS2-EBZ (AD9361), still it is easier to burn image to sd card first )
https://wiki.analog.com/resources/tools-software/linux-software/adi-kuiper_images/release_notes

wget https://swdownloads.analog.com/cse/kuiper/image_2023-12-13-ADI-Kuiper-full.zip
# download balena etcher
https://github.com/balena-io/etcher/releases/
sudo yum localinstall balena-etcher-***.x86_64.rpm
# then flash the image using balena

For the zynqmp projects copy these files to the root of the BOOT FAT32 partition (target is `zynqmp-zcu102-rev10-ad9695`):

target/BOOT.BIN
target/<specific_folder>/system.dtb
zynqmp-common/Image

* bit and xsa file (not needed if downloaded in first step)

# source vivado 2022.1
https://github.com/analogdevicesinc/hdl/releases
git clone https://github.com/analogdevicesinc/hdl  -b 2022_R2 
cd hdl/projects/ad9695_fmc/
make

xsa inside ./hdl/projects/ad9695_fmc/zcu_102/ad9695_fmc_zcu102.sdk/
copy xsa to some folder

* boot files (not needed if downloaded in first step)
* Image & system.dtb
https://wiki.analog.com/resources/tools-software/linux-drivers-all
https://wiki.analog.com/resources/tools-software/linux-build/generic/zynqmp

sudo snap install uboot-tools
wget https://raw.githubusercontent.com/analogdevicesinc/wiki-scripts/master/linux/build_zynqmp_kernel_image.sh 
chmod +x build_zynqmp_kernel_image.sh 
./build_zynqmp_kernel_image.sh zynqmp xilinx/zynqmp-zcu102-rev10-ad9695.dtb
mv zynqmp-zcu102-rev10-ad9695.dtb system.dtb

copy Image & system.dtb to same folder

build_zynqmp_kernel_image.sh

#!/bin/bash
set -e

# Usage: build_zynq_kernel_image.sh [kernel_dir] [dt_file] [path_cross_toolchain]
#  If no dt_file is specified, the default is `xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb`
#  If no CROSS_COMPILE specified, a GCC toolchain will be downloaded
#  from Linaro's website and used.
#  Default host for Linaro's toolchain is assumed x86_64 but it can be
#  overriden with `HOST=i686 ./build_zynq_kernel_image.sh [opts]`
#
# Notes:
# - it's recommened to run this into a build dir, to make things easier to cleanup
# - this script is not particularly good at tolerating interruptions,
#   so, if you decide to interrupt this mid-way, you may need to cleanup stuff
#

LINUX_DIR="${1:-linux-adi}"
DTFILE="$2"
CROSS_COMPILE="$3"

HOST=${HOST:-x86_64}

DEFCONFIG=${DEFCONFIG:-adi_zynqmp_defconfig}
GCC_ARCH=aarch64-linux-gnu
IMG_NAME="Image"
ARCH=arm64
DTDEFAULT=xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb

[ -n "$NUM_JOBS" ] || NUM_JOBS=5

# if CROSS_COMPILE hasn't been specified, go with a few defaults
[ -n "$CROSS_COMPILE" ] || {
	CROSS_COMPILE=${GCC_ARCH}-gcc
	if type "${GCC_ARCH}-gcc" >/dev/null 2>&1 ; then
		CROSS_COMPILE="${GCC_ARCH}-"
	else
		GCC_VERSION="8.3-2019.03"
		GCC_DIR="gcc-arm-${GCC_VERSION}-${HOST}-${GCC_ARCH}"
		GCC_TAR="$GCC_DIR.tar.xz"
		GCC_URL="https://developer.arm.com/-/media/Files/downloads/gnu-a/${GCC_VERSION}/binrel/${GCC_TAR}"
		if [ ! -d "$GCC_DIR" ] && [ ! -e "$GCC_TAR" ] ; then
			wget "$GCC_URL"
		fi
		if [ ! -d "$GCC_DIR" ] ; then
			tar -xvf $GCC_TAR || {
				echo "'$GCC_TAR' seems invalid ; remove it and re-download it"
				exit 1
			}
		fi
		CROSS_COMPILE=$(pwd)/$GCC_DIR/bin/${GCC_ARCH}-
	fi
}

# FIXME: remove the line below once Talise & Mykonos APIs
#        dont't use 1024 bytes on stack
KCFLAGS="$KCFLAGS -Wno-error=frame-larger-than="
export KCFLAGS

# FIXME: remove this function once kernel gets upgrade and
#        GCC doesn't report these warnings anymore
GCC="${CROSS_COMPILE}gcc"
if [ "$($GCC -dumpversion | cut -d. -f1)" -ge "8" ]; then
	KCFLAGS="$KCFLAGS -Wno-error=stringop-truncation"
	KCFLAGS="$KCFLAGS -Wno-error=packed-not-aligned"
	KCFLAGS="$KCFLAGS -Wno-error=stringop-overflow= -Wno-error=sizeof-pointer-memaccess"
	KCFLAGS="$KCFLAGS -Wno-error=missing-attributes"
fi

if [ "$($GCC -dumpversion | cut -d. -f1)" -ge "9" ]; then
	KCFLAGS="$KCFLAGS -Wno-error=address-of-packed-member -Wno-error=stringop-truncation"
fi
export KCFLAGS

# Get ADI Linux if not downloaded
# We won't do any `git pull` to update the tree, users can choose to do that manually
[ -d "$LINUX_DIR" ] || \
	git clone https://github.com/analogdevicesinc/linux.git "$LINUX_DIR"

export ARCH
export CROSS_COMPILE

pushd "$LINUX_DIR"

make $DEFCONFIG

make -j$NUM_JOBS $IMG_NAME UIMAGE_LOADADDR=0x8000

if [ -z "$DTFILE" ] ; then
	echo
	echo "No DTFILE file specified"
	echo
else
	make $DTFILE
fi

popd 1> /dev/null

cp -f $LINUX_DIR/arch/$ARCH/boot/$IMG_NAME .
[ -z "$DTFILE" ] || \
	cp -f $LINUX_DIR/arch/$ARCH/boot/dts/$DTFILE .

echo "Exported files: $IMG_NAME, $DTFILE"

* boot files (not needed if downloaded in first step)
* uboot.elf

* boot files (not needed if downloaded in first step)
* BOOT.BIN

sudo snap install uboot-tools
wget https://raw.githubusercontent.com/analogdevicesinc/wiki-scripts/master/zynqmp_boot_bin/build_zynqmp_boot_bin.sh
chmod +x build_zynqmp_boot_bin.sh
# add arm gcc downloaded by previous step to path 
export PATH="/home/alpsark/Music/Projects/analog-devices-adc/2_Image_and_dtb/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu/bin:$PATH"
./build_zynqmp_boot_bin.sh ../zcu_hdl_22.1/projects/ad9695_fmc/zcu102/ad9695_fmc_zcu102.sdk/system_top.xsa u-boot.elf(from ./zynqmp-zcu102-rev10-ad9695/bootgen_sysfiles.tgz) image download 

build_zynqmp_kernel_image.sh

#!/bin/bash
set -ex

HDF_FILE=$1
UBOOT_FILE=$2
ATF_FILE=${3:-download}
BUILD_DIR=build_boot_bin
OUTPUT_DIR=output_boot_bin

usage () {
	echo "usage: $0 system_top.<hdf/xsa> u-boot.elf  (download | bl31.elf | <path-to-arm-trusted-firmware-source>) [output-archive]"
	exit 1
}

depends () {
	echo "Xilinx $1 must be installed and in your PATH"
	echo "try: source /opt/Xilinx/Vivado/201x.x/settings64.sh"
	exit 1
}

### Check command line parameters
echo $HDF_FILE | grep -q ".hdf\|.xsa" || usage
echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" -e "u-boot" || usage

if [ ! -f $HDF_FILE ]; then
	echo $HDF_FILE: File not found!
	usage
else
	if [[ "$HDF_FILE" =~ ".hdf" ]]; then TOOL="xsdk";else TOOL="vitis";fi
fi

if [ ! -f $UBOOT_FILE ]; then
    echo $UBOOT_FILE: File not found!
    usage
fi

### Check for required Xilinx tools (starting with 2019.2 there is no hsi anymore)
command -v xsct >/dev/null 2>&1 || depends xsct
command -v bootgen >/dev/null 2>&1 || depends bootgen
if [[ "$HDF_FILE" =~ ".hdf" ]];then (command -v hsi >/dev/null 2>&1 || depends hsi);fi

rm -Rf $BUILD_DIR $OUTPUT_DIR
mkdir -p $OUTPUT_DIR
mkdir -p $BUILD_DIR

# 2017.4 use 47af34b94a52b8cdc8abbac44b6f3ffab33a2206
# 2018.1 use df4a7e97d57494c7d79de51b1e0e450d982cea98
# 2018.2 use 93a69a5a3bc318027da4af5911124537f4907642
# 2018.3 use 08560c36ea5b6f48b962cb4bd9a79b35bb3d95ce
# 2019.3 use 713dace94b259845fd8eede11061fbd8f039011e
# 2020.1 use bf72e4d494f3be10665b94c0e88766eb2096ef71
# 2021.2 use 799131a3b063f6f24f87baa74e46906c076aebcd
# 2022.2 use 5ebf70ea38e4626637568352b644acbffe3b13c1

tool_version=$($TOOL -version | sed -n '3p' | cut -d' ' -f 3)
if [ -z "$tool_version" ] ; then
	echo "Could not determine Vivado version"
	exit 1
fi
atf_version=xilinx-$tool_version

if [[ "$atf_version" == "xilinx-v2021.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1";fi
if [[ "$atf_version" == "xilinx-v2021.1.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1_update1";fi
if [[ "$atf_version" == "xilinx-v2021.2" ]];then atf_version="xilinx-v2021.2";fi
if [[ "$atf_version" == "xilinx-v2022.2" ]];then atf_version="xilinx-v2022.2";fi

if [[ "$4" == "uart1" ]];then console="cadence1";else console="cadence0";fi

### Check if ATF_FILE is .elf or path to arm-trusted-firmware
if [ "$ATF_FILE" != "" ] && [ -d $ATF_FILE ]; then
### Build arm-trusted-firmware bl31.elf
(
	cd $ATF_FILE
	make distclean
	git checkout $atf_version
	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console
)
	cp $ATF_FILE/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
elif [ "$ATF_FILE" == "download" ]; then
(
	command -v git >/dev/null 2>&1 || depends git
	cd $BUILD_DIR
	git clone https://github.com/Xilinx/arm-trusted-firmware.git
	cd arm-trusted-firmware
	git checkout $atf_version
	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console
)
	cp $BUILD_DIR/arm-trusted-firmware/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
else
	echo $ATF_FILE | grep -q -e "bl31.elf" || usage
	if [ ! -f $ATF_FILE ]; then
		echo $ATF_FILE: File not found!
		usage
	fi
	cp $ATF_FILE $OUTPUT_DIR/bl31.elf
fi

cp "$HDF_FILE" "$BUILD_DIR/"
cp "$UBOOT_FILE" "$OUTPUT_DIR/u-boot.elf"
cp "$HDF_FILE" "$OUTPUT_DIR/"

# Work-around for MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change
# (https://www.xilinx.com/support/answers/71961.html)
if [ $tool_version == "v2018.3" ];then
(
	wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR
	unzip $BUILD_DIR/72113-files.zip -d  $BUILD_DIR
)
fi

### Create create_fsbl_project.tcl file used by xsct to create the fsbl.
echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl
echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl
### The fsbl creating flow is different starting with 2019.2 Xilinx version
if [[ "$HDF_FILE" =~ ".hdf" ]];then
        echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
        echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
        echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
        echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
	if [ $tool_version == "v2018.3" ];then
		echo "file copy -force xfsbl_ddr_init.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
		echo "file copy -force xfsbl_hooks.c    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
		echo "file copy -force xfsbl_hooks.h    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
	fi
	echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl

	### Create create_pmufw_project.tcl
	echo "set hwdsgn [open_hw_design `basename $HDF_FILE`]" > $BUILD_DIR/create_pmufw_project.tcl
	echo 'generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -compile -sw pmufw -dir pmufw' >> $BUILD_DIR/create_pmufw_project.tcl
	echo 'quit' >> $BUILD_DIR/create_pmufw_project.tcl

        FSBL_PATH="$BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf"
        SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw_0/system_top.bit"
	PMUFW_PATH="$BUILD_DIR/pmufw/executable.elf"
else
	# Flow got changed starting with 2019.2 version (when Vitis replaced SDK) and pmufw is generated automatically with fsbl
        echo 'platform create -name hw0 -hw system_top.xsa -os standalone -out ./build/sdk -proc $cpu_name' >> $BUILD_DIR/create_fsbl_project.tcl
        echo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl

        FSBL_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf"
        SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw0/hw/system_top.bit"
	PMUFW_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/pmufw.elf"
fi

### Create zynq.bif file used by bootgen
echo "the_ROM_image:" > $OUTPUT_DIR/zynq.bif
echo "{" >> $OUTPUT_DIR/zynq.bif
echo "[bootloader,destination_cpu=a53-0] fsbl.elf" >> $OUTPUT_DIR/zynq.bif
echo "[pmufw_image] pmufw.elf" >> $OUTPUT_DIR/zynq.bif
echo "[destination_device=pl] system_top.bit" >> $OUTPUT_DIR/zynq.bif
echo "[destination_cpu=a53-0,exception_level=el-3,trustzone] bl31.elf" >> $OUTPUT_DIR/zynq.bif
echo "[destination_cpu=a53-0, exception_level=el-2] u-boot.elf" >> $OUTPUT_DIR/zynq.bif
echo "}" >> $OUTPUT_DIR/zynq.bif

### Build fsbl.elf & pmufw.elf
(
	cd $BUILD_DIR
	xsct create_fsbl_project.tcl
	if [[ "$HDF_FILE" =~ ".hdf" ]];then
		hsi -source create_pmufw_project.tcl
		### There was a bug in some vivado version where they build would fail -> check CC_FLAGS
		grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile
		cd pmufw
		make
	fi
)
### Copy fsbl and system_top.bit into the output folder
cp "$FSBL_PATH" "$OUTPUT_DIR/fsbl.elf"
cp "$SYSTEM_TOP_BIT_PATH" "$OUTPUT_DIR/system_top.bit"
cp "$PMUFW_PATH" "$OUTPUT_DIR/pmufw.elf"

### Build BOOT.BIN
(
	cd $OUTPUT_DIR
	bootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w
)

### Optionally tar.gz the entire output folder with the name given in argument 4/5
if [[ ( $4 == "uart"* && ${#5} -ne 0 ) ]]; then
	tar czvf $5.tar.gz $OUTPUT_DIR
fi

if [[ ( ${#4} -ne 0 && $4 != "uart"* && ${#5} -eq 0 ) ]]; then
        tar czvf $4.tar.gz $OUTPUT_DIR
fi

## Using Kuiper Linux

hostname : analog
username : root
pass : analog

https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux

There are two things to check when making sure your system is setup properly.

* The platform is booting to Kuiper Linux
* The hardware configuration files are correct

When the platform running Kuiper Linux is powered up, any IIO devices present and enabled in the configuration file, will be displayed in the terminal window by running the `iio_info` command, this is a good way to verify that the hardware and device drivers loaded properly.

## Multichannel System Clocking Device



### for ssh:

hostname : analog
username : root
pass : root

### for programming gui:

The Raspberry Pi inside AD-SYNCHRONA14-EBZ runs the RaspAP, which is an application that gives access to the GUI. The General Page of the GUI allows users to enable/disable channels, and set the frequencies on each channel.

For gui pasting ip address is enough, The default username is **admin** and the password is **analog**.

==== Clock Output Configuration ====

There are a total of 14 high speed clocks that come out of the final clock mux; these can range from 2150 MHz to 3550 MHz in different modes and connection schemes. The maximum clock output is 2400 MHz, which can be divided down by 1, 2, 3, 4, 5, 6, and even numbers up to 4094. Moreover, the output clock resolution depends on the “Clock Distribution Frequency”, and the divider value.

The outputs are hardware configurable as **LVPECL**, **LVDS**, and **CMOS**.

|Name|**Maximum Operating Frequency**|
| -------- | -------- |
| **LVPECL** | 2400 MHz (3 dB bandwidth) |
| **LVDS** | 1700 MHz |
| **CMOS** | 600 MHz |

The table below shows the default configuration:

| HMC7044 Pin Name | Enclosure Designator | Board Connector Designator |Default Configuration |
| -------- | -------- |-------- |-------- |
| CLKOUT0 | CH11 | P6 | LVPECL AC-COUPLED |
| CLKOUT1 | CH12 | P5 | LVPECL AC-COUPLED |
| CLKOUT2 | CH14 | P3 | LVPECL DC-COUPLED |
| CLKOUT3 | CH13 | P4 | LVPECL DC-COUPLED |
| CLKOUT4 | CH8 | J9 (P\), J11 (N) | CMOS |
| CLKOUT5 | CH10 | J12 (P\), J15 (N)| LVPECL AC-COUPLED |
| CLKOUT6 | CH6 | J13 (P\), J16 (N) | CMOS |
| CLKOUT7 | CH4 | J10 (P\), J14 (N)| LVDS AC-COUPLED |
| CLKOUT8 | CH1 | J17 (P\), J18 (N)| LVDS AC-COUPLED |
| CLKOUT9 | CH2 | J19 (P\), J20 (N) | LVDS AC-COUPLED |
| CLKOUT10 | CH3 | J1 (P\), J2 (N) | LVDS AC-COUPLED |
| CLKOUT11 | CH5 | J3 (P\), J4 (N) | CMOS |
| CLKOUT12 | CH9 | J5 (P\), J7 (N) | LVPECL AC-COUPLED |
| CLKOUT13 | CH7 | J6 (P\), J8 (N) | CMOS |

The default configuration can be changed. Each channel has all the footprints for the passive components.