---
# System prepended metadata

title: Lab 9

---

# Lab 9
Name: M Akash
Roll No.: CS22B037

---
## Question 1

**Code**
```verilog=
module ALU(input [3:0]a,b,[1:0]select, output reg [3:0]y);
always @(*)
begin
case(select)
	2'b00: y=a+b;
	2'b01: y=a-b;
	2'b10: y=a&b;
	2'b11: y=a|b;
endcase
end
endmodule

module ALU_testbench();
reg [3:0]a,b;
reg [1:0]select;
wire [3:0]out;
ALU DUT1(.a(a),.b(b),.select(select),.y(out));
initial
	begin
			a=7;b=2;select=2'b00;
		#100    select=2'b01;
		#100    select=2'b10;
		#100    select=2'b11;
	end
endmodule
```

**Output:**
![Screenshot 2024-04-07 171433](https://hackmd.io/_uploads/S1rNWFWe0.png)



---
## Question 2
**Code**
```verilog=
module simple_processor (input [7:0] instruction, output reg [31:0] reg_file_out, output reg [63:0] memory_out);
reg [7:0] memory [7:0]; // 8 bytes of memory
reg [7:0] reg_file [3:0]; // 4 general-purpose 8-bit registers
reg [1:0] src_register;
reg [2:0] offset;
reg [1:0] dest_register;
reg op;
assign src_register = instruction[1:0];
assign offset = instruction[4:2];
assign dest_register = instruction[6:5];
assign op = instruction[7];
integer i, j;

initial begin
    for (i = 0; i < 64; i = i + 1) begin
        memory[i] = 8'b0;    //initializing memory with 0
    end
end
initial begin
    for (i = 0; i < 4; i = i + 1) begin
        reg_file[i] = 8'b10000010;     //initializing registers with 10000010
    end
end

always @(*) begin
	if(op == 1'b0) begin //lw
		//for (i = 0; i < 8; i = i + 1) begin
        		memory[dest_register-1] = reg_file[offset+src_register-1];
    		//end
	end
	else if(op == 1'b1) begin //sw
		//for (i = 0; i < 8; i = i + 1) begin
        		reg_file[offset+src_register-1] = memory[dest_register-1];
    		//end
	end
end
always @(*) begin
    for (i = 0; i < 4; i = i + 1) begin
	for(j = 0; j < 8; j = j + 1) begin
        	reg_file_out[i*8+j] = reg_file[i][j];
	end
    end
end

always @(*) begin
    for (i = 0; i < 8; i = i + 1) begin
	for(j = 0; j < 8; j = j + 1) begin
        	memory_out[i*8+j] = memory[i][j];
	end
    end
end

endmodule

module simple_processor_testbench();
reg [7:0] instruction;
wire [63:0] memory_out;
wire [31:0] reg_file_out;
simple_processor DUT1(.instruction(instruction), .reg_file_out(reg_file_out), .memory_out(memory_out));
initial
	begin 
                    	instruction = 8'b01001101;    // lw R2, 3(R1)
		#100    instruction = 8'b11101101;    // sw R3, 3(R1)
	end
endmodule

```

**Output:**
![Screenshot 2024-04-08 021324](https://hackmd.io/_uploads/HkU5bFZeA.png)

**Observation:**
- _1. There is 8 bytes of memory and each byte has 8 bits, so total 64 bits of memory, and last 8 bits of memory_out represents 1st byte and so on..._
_2. There are 4 registers and each register can store 8 bits, so total 32 bits of blocks, last 8 bits of reg_file_out represents 1st register and so on..._
- lw R2, 3(R1) loades register 4 value in 2nd memory byte.
- sw R3, 3(R1) stores 3rd byte memory in register 4.


---
## Question 3

**Code**
```c=
#include<stdio.h>

// Sum of Array elememts
int sum(int arr[], int n){
    int s=0;
    for(int i=0; i<n; i++){
        s+=arr[i];
    }
    return s;
}

int main(){
    int n;
    printf("Enter value of n: ");
    scanf("%d",&n);
    int arr[n];
    printf("Enter elements of array: ");
    for(int i=0; i<n; i++){
        scanf("%d",&arr[i]);
    }
    printf("Sum of all elements is %d\n",sum(arr,n));
    return 0;
}
```

**Output:**
![Screenshot from 2024-04-08 17-55-41](https://hackmd.io/_uploads/B1p9HY-xC.png)
- 1,41,706 instructions are executed to calculate sum of first 5 natural numbers. Similarly 1,51,757 instructions for first 20 numbers.

