# Meeting Notes

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## Tuesday, May 30, 2023

3 further meetings (part of continuous evaluation), if we need help we can also have more

Final paper evaluation: have we grasped the idea of TPU, match stuff from lecture to TPU (data movements, buffers, …)

20h in total expected (six weeks)

4 versions of TPU
Paper for version 4 is open
Paper on first generation is a blog
David … - godfather of architecture - in one of the books TPUs are described as far as they are allowed to described
One option: try analyse the evolution of TPUs over the years, what where the goals of these evolutions
Additionally look how they utilise sparsity and mixed precision
Transformers -> lots of zeros -> sparsity
Details on sparsity would be great, otherwise why it is important
Moving data costs energy and speed -> zero elements (sparsity) do not have to be moved

Why decisions were made in the evolution of TPUs? Why they made sense? Were they good or bad in our opinion? Why?

If we have time or do not find enough on TPUs, we could look into differences between main architecture versus edge TPUs.

Next meeting:
(Text him towards end of next week for scheduling next meeting)
- Gather four papers/blog posts
- Try to read at least abstracts and conclusions
- Try to make layout of seminar work (how it will look like)

Template:
https://stackoverflow.com/questions/33971693/latex-ieee-template-use-single-column-table-in-multicolumn-latex-content

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## Thursday, June 8, 2023

* Numerical representation?
* Only stick with what we see in the articles, don't go much further
* Floorplanning?
* Can be a separate section that looks at the one interesting article we found
* Memory and access to data
* Have to see if there is an article that talks about the TPU specifically, because we have not seen anything yet
* Reconfigurable Optical Switches
* Probably keep this in the history unless we find a really good article explaining the motivation and (simple) theory behind such decisions
* Break down our main body into two sections probably:
* History of the TPU versions
* Relevant and interesting related material

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## Monday, Jun 12, 2023

In the future, we should have this open while we talk with Durillo

**Example for v0:**
Compute what you need for an example workload. E.g. we want to have a workload of 1 Petaflops. How many MUX do we need. How much memory?
Focus on how the operations are done.

Try it in systolic array simulator. (He will send a link to us, remind him tomorrow if he doesn’t do it) (If we get lost/need material that describes what we need to do, ask him)
https://scalesim-project.github.io/

Comparison of TPU, GPU, CPU

-> Use this as an example in section on v0

Leave PaLM aside, would be too much to explain details.

* TPU
* Which operations are accelerated
* How many cores/TPUS needed for a specific network?
* Focus on details of how to solve a specific need / how to approach things. We could do our own estimation
* RISC vs CISC
* TensorCores and MXU Cores
* What datatypes and memory types are supported? Did it change across versions?
*

**Next Meeting:**
- Schedule as we want (2 weeks to 20 days), keep in mind that we need content for another one afterwards (so papers collected for v1 and/or v2/v3)
- Have v0 and v1 completed or almost completed

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## Meeting Wednesday, June 21, 2023

* Need to figure out when to talk to Durillo again, and about what
* Sometime middle of next week
* Wednesday midday or afternoon is best for us
* How we distribute work
* Timm does a bit more on the Introduction
* Timm works on 2 informal topics
* Google's scaling problems
* From CPUs and GPUs to Domain Specific Architectures
* Simon looks at the systolic array simulator, and some technical stuff
* We should do a quick progress report on Friday

## Meeting Wednesday, July 11, 2023

* Went over paper, happy to send this off but want a few small corrections.
* Timm will add some sentences on power in v1
* Discussion on presentation:
* Both 27 and 28 are fine, but Simon prefers Thursday.
* Things to add:
* References
* Page numbers
*
* Intro Slide: Title and Names (Both)
* Motivation for DSAs (Timm)
* Table of changing workloads
* CPUs vs GPUs vs TPUs
* Systolic Arrays (Simon)
* 2 slides
* v1 (Simon)
* Fig 3
* Instructions
* Roofline (goes to v2/v3)
* v2/v3 (Timm)
* Design consderations for the v2
* Use the figure that transforms from v1 to v2
* v4 (Both)
* Cooling and v4i (Simon)
* OSCs (Simon)
* SparseCores (Timm)
* QA
* Supplmentary slide (for when people ask hard stuff)
* Compiler (v2/v3)
* Torus structure
* Send to Durillo for review, but we won't change anything big