---
# System prepended metadata

title: 從0到有製作自己的CPU！！ 第五周活動記錄 20220804
tags: [' 伴學松', ' 伴學松活動記錄', RISCV]

---

---
tags: RISCV, 伴學松, 伴學松活動記錄
---
# 從0到有製作自己的CPU！！ 第五周活動記錄 20220804

[TOC]

# 直播紀錄連結

{%youtube snh22qx3etM%}

## 出席
- [x] KIM_WENG
- [x] 名名
- [ ] chuan
- [ ] bill503084699
- [ ] 楓糖
- [x] 謝祥辰
- [x] 黑貓
- [x] sixkwnp
- [ ] Bonki
- [x] ouo314
- [x] Willwho
- [x] GYLABA
- [x] mikuthebest
- [x] Penquuin
- [x] 葉子
- [ ] painCake
- [ ] EZ4ENCE
- [ ] 頂漿汗腺
- [ ] 角角
- [ ] adam chen

# 討論內容
1. 下禮拜是不是需要上板子
2. 討論這次伴伴學 ALU,Decoder,Register 之 [RV32I 標準與架構](https://github.com/orgs/accomdemy/repositories)
3. 祥辰的Code跑的Testbench結果圖
![](https://i.imgur.com/Eg8FMYY.png)
![](https://i.imgur.com/cyrb0hO.png)
[name=謝祥辰]
4. 討論下周內容
5. 介紹 Instruction memory

# 本周作業
1. 利用Verilog 實現 Decoder, imm, Register, ALU 電路，並 Testbench 測試看看

# 討論重點
1. 採用哪個學友的 ALU.v 去向下寫
2. 修改 R type, I type 的 ALU.v
3. 修改 Register.v
4. 修改 CPU.v
5. Testbench 半成品
6. 下周討論 Instruction memory & PC

## 點子 / 撇步
- 選哪些指令
- 修改指令 & 排版
[name=黑貓]
- imm怎麼運作 ; A: 只是變數不從 register 拿而是 decoder 給而已
[name=DCtime, 名名]
- [name=Kim Weng]
![](https://i.imgur.com/LRSy0ik.png)
- Q & A

# 補充
- **[名名寫的，黑貓修改過的 Code](https://github.com/accomdemy/accomdemyrv32i)**
- **Will 寫的 ALU.v** (alu_tb.v)
```verilog=
module alu_tb();
    reg [16:0] full_op; // func7(7)+func3(3)+op(7)
    reg [31:0] in1;
    reg [31:0] in2;
    wire [31:0] out;
    
    alu cpu(full_op, in1, in2, out);

    initial begin
    full_op = 17'b0; in1 = 32'b0; in2 = 32'b0;
    
    #1 full_op = 17'b00000000000110011; in1 = 32'hff; in2=32'hff00; // add ff + ff00 = ffff
    #1 full_op = 17'b01000000000110011; in1 = 32'hff; in2=32'hcc; // sub ff - cc = 33
    #1 full_op = 17'b01000000000010011; in1 = 32'hff; in2=32'hcc; // subi should be error
    #1 full_op = 17'b00000000010110011; in1 = 32'hff; in2=32'd4; // sll ff << 4 = ff0
    #1 full_op = 17'b00000000100110011; in1 = 32'hff; in2=32'hf; // slt ff < f = 0
    #1 full_op = 17'b00000000100110011; in1 = 32'hff; in2=32'hfff; // slt ff < fff = 1
    #1 full_op = 17'b00000000100110011; in1 = 32'd1; in2=-32'd1; // slt 1 < -1 = 0
    #1 full_op = 17'b00000000100110011; in1 = -32'd10; in2=-32'd1; // slt -10 < -1 = 1
    #1 full_op = 17'b00000000110110011; in1 = -32'd1; in2=32'd1; // sltu -1(ffffffff) < 1(00000001) = 0
    #1 full_op = 17'b00000000110110011; in1 = -32'd10; in2=-32'd1; // sltu -10(fffffff6) < -1(ffffffff) = 1
    #1 full_op = 17'b00000001000110011; in1 = 32'hff00f0f0; in2=32'h00ffff00; // xor ff00f0f0 ^ 00ffff00 = 0000f0f0
    #1 full_op = 17'b00000001010110011; in1 = 32'hff00f0f0; in2=32'd8; // srl ff00ffff >> 8 = 00ff00f0
    #1 full_op = 17'b01000001010110011; in1 = 32'hff00f0f0; in2=32'd8; // sra ff00ffff >> 8 = ffff00f0
    #1 full_op = 17'b01000001010110011; in1 = 32'hff00f0f0; in2=32'd16; // sra ff00ffff >> 16 = ffffff00
    #1 full_op = 17'b00000001100110011; in1 = 32'h00ff00ff; in2=32'hff0000ff; // or 00ff00ff | ff0000ff = ffff00ff
    #1 full_op = 17'b00000001110110011; in1 = 32'h00ff00ff; in2=32'hff0000ff; // and 00ff00ff & ff0000ff = 000000ff



    #1 $stop;
    end

endmodule
```

