---
# System prepended metadata

title: 軟硬體協同作業-HW2

---

# **軟硬體協同設計**
**作業二：BCD
學號：A1095140
姓名：盧冠宇
指導老師：林宏益**
## **一、實驗目的**
	用VScode撰寫BCD Decoder的Verilog程式，再用Vivado執行並觀看波形檔、schematic圖、power等數據。
## 二、實驗步驟
### Verilog :
* ### BCD
>
	module BCDRTL(in, out, reset, preset);
	input   reset, preset;
    input [3:0] in;
    output  [9:0] out;

    //reg [9:0] a;
	reg [9:0] out;

	always @(in or reset or preset )
    begin
        if (reset == 0)
            out = 0;
        else if (reset == 1 && preset == 1)
            out = 15;
        else
        case (in [3:0])
                4'b0000 : out = 10'b1111111110;
                4'b0001 : out = 10'b1111111101;
                4'b0010 : out = 10'b1111111011;
                4'b0011 : out = 10'b1111110111;
                4'b0100 : out = 10'b1111101111;
                4'b0101 : out = 10'b1111011111;
                4'b0110 : out = 10'b1110111111;
                4'b0111 : out = 10'b1101111111;
                4'b1000 : out = 10'b1011111111;
                4'b1001 : out = 10'b0111111111;
                4'b1010 : out = 10'b1111111111;
                4'b1011 : out = 10'b1111111111;
                4'b1100 : out = 10'b1111111111;
                4'b1101 : out = 10'b1111111111;
                4'b1110 : out = 10'b1111111111;
                4'b1111 : out = 10'b1111111111;
         endcase
    end

endmodule
*  ### Testbench
>
`timescale 1ns/1ps
module BCDRTL_tb;
  reg  [3:0] in;
  reg  reset, preset;
  wire [9:0] out;
  BCDRTL BCDRTL(in, out, reset, preset);
  initial
    begin
      $dumpfile("BCDRTL.vcd");
      $dumpvars(0,BCDRTL_tb);
      $monitor("in = %b | reset = %b | preset = %b | out = %b",in,reset,preset,out);
      #0    in = 4'b0000; reset = 1; preset = 0;
      #4    in = 4'b0001; 
      #4    in = 4'b0010; 
      #4    in = 4'b0011; 
      #4    in = 4'b0100; 
      #4    in = 4'b0101; 
      #4    in = 4'b0110;
      #4    in = 4'b0111;
      #4    in = 4'b1000;
      #4    in = 4'b1001;
      #4    in = 4'b1010;
      #4    in = 4'b1011;
      #4    in = 4'b1100;
      #4    in = 4'b1101;
      #4    in = 4'b1110;
      #4    in = 4'b1111;
      #4    in = 4'b0000; reset = 0; preset = 0;
      #4    in = 4'b0001; 
      #4    in = 4'b0010; 
      #4    in = 4'b0011; 
      #4    in = 4'b0100; 
      #4    in = 4'b0101; 
      #4    in = 4'b0110;
      #4    in = 4'b0111; preset = 1;
      #4    in = 4'b1000;
      #4    in = 4'b1001;
      #4    in = 4'b1010;
      #4    in = 4'b1011;
      #4    in = 4'b1100;
      #4    in = 4'b1101;
      #4    in = 4'b1110;
      #4    in = 4'b1111;
      #4    in = 0; reset = 1; preset = 1;
      #4    in = 1; 
      #4    in = 2; 
      #4    in = 3; 
      #4    in = 4; 
      #4    in = 5; 
      #4    in = 6;
      #4    in = 7;
      #4    in = 8;
      #4    in = 9;
      #4    in = 10;
      #4    in = 11;
      #4    in = 12;
      #4    in = 13;
      #4    in = 14;
      #4    in = 15;
     #4 $finish;
    end

endmodule
## 三、實驗結果	
1. 波形圖
![](https://hackmd.io/_uploads/H1fw4JXZa.png)
![](https://hackmd.io/_uploads/H1sDVJQZ6.png)
![](https://hackmd.io/_uploads/rJNOVkX-a.png)
2. RTL圖![](https://hackmd.io/_uploads/Sy-T417ba.png)

3. schematic圖
![](https://hackmd.io/_uploads/H1OaEy7WT.png)
![](https://hackmd.io/_uploads/r1ZAEymbT.png)
4. power
![](https://hackmd.io/_uploads/SyI5B1m-T.png)
![](https://hackmd.io/_uploads/rkIjHJm-T.png)
5. 討論
根據vivado的報告，可以發現的電路圖和schematic圖不一致，RTL是由一個唯讀記憶體ROM與兩個MUX組成，schematic的電路是由inverter和查找表組成，而power的部分，我發現我的power和陳弘喻同學的不同，所以我將前面的ROM改成用邏輯閘組成，跑完後發現power沒有改善，所以基本可以確定是Latch的問題，至於原因我認為是因為有了Latch用Clk來形成一個閘門，使電路不用一直消耗功率去輸出，來降低I/O的power。
6. FPGA影片
[https://youtu.be/ys9KY8cyvgo?si=Cy46cpidt-P9Jttx](https://)





## 四、實驗心得
### 這次的作業是做一個BCD decoder ，由於上次已經將vivado裝好了所以這次的作業很快的就完成，但在看報告時發現我的power和陳弘喻同學的不同，我的大很多，看過他的程式碼與對自己程式碼的各部分分別更改後發現是Latch的問題，經過這次的實驗後我學會了何種構寫verilog的方式可以的到較小的power。

