---
# System prepended metadata

title: Lab Report Module 6 - LFSR (Linear Feedback Shift Register)

---

# Lab Report Module 6 - LFSR (Linear Feedback Shift Register)
```
Name    : Evandra Rasya Fadhillah
NPM     : 2406450352
```

## Task 1 Implementation Questions

### 1. VHDL Entity and Architecture Code [25 points]

**Instructions:** Submit your complete VHDL code for the 8-bit LFSR. If you found any errors or problems from your Case Study implementation, please provide the corrected code here.

**LFSR Specifications Reminder:**
- 8-bit LFSR with feedback: `feedback = bit[7] XOR bit[5] XOR bit[4] XOR bit[3]`
- Must use FOR LOOP to calculate XOR feedback
- Shift operation: right shift with feedback going to bit 7
- Output random_bit = bit 0 (rightmost bit that comes out)

**Submit your complete VHDL code here:**

```vhdl
-- Place your complete lfsr_8bit entity and architecture code here
-- Include both entity declaration and behavioral architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lfsr_8bit is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        enable : in std_logic;
        seed : in std_logic_vector(7 downto 0);
        lfsr_out : out std_logic_vector(7 downto 0);
        random_bit : out std_logic);
end lfsr_8bit;

architecture Behavioral of lfsr_8bit is
    signal lfsr_reg : std_logic_vector(7 downto 0) := (others => '0');
begin

process(clk)
    variable feedback : std_logic;
    variable temp : std_logic_vector(7 downto 0);
begin
    if rising_edge(clk) then
        if reset = '1' then
            lfsr_reg <= seed;
        elsif enable = '1' then
            feedback := '0';

            for i in 0 to 7 loop
                if (i = 7) or (i = 5) or (i = 4) or (i = 3) then
                    feedback := feedback xor lfsr_reg(i);
                end if;
            end loop;

            temp(7) := feedback;
            temp(6 downto 0) := lfsr_reg(7 downto 1);
            lfsr_reg <= temp;
        end if;
    end if;
end process;

lfsr_out <= lfsr_reg;
random_bit <= lfsr_reg(0);

end Behavioral;

```

### 2. Testbench Code [25 points]

**Testbench Requirements:**
Create a testbench that:
1. Set seed = "10110100", reset = '1' for 1 cycle
2. Set reset = '0', enable = '1' (optional), run for 15 clock cycles

**Submit your testbench code here:**

```vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_lfsr_8bit is
end tb_lfsr_8bit;

architecture sim of tb_lfsr_8bit is
    signal clk : std_logic := '0';
    signal reset : std_logic := '0';
    signal enable : std_logic := '0';
    signal seed : std_logic_vector(7 downto 0) := "10110100";
    signal lfsr_out : std_logic_vector(7 downto 0);
    signal random_bit : std_logic;
    constant T : time := 10 ns;
begin

    clk <= not clk after T / 2;

    uut: entity work.lfsr_8bit
        port map (
            clk => clk,
            reset => reset,
            enable => enable,
            seed => seed,
            lfsr_out => lfsr_out,
            random_bit => random_bit);

    stim: process
    begin
        reset <= '1';
        enable <= '0';
        wait for T;

        reset <= '0';
        enable <= '1';
        wait for 15 * T;

        enable <= '0';
        wait for 5 * T;

        wait;
    end process;

end sim;

```

### ModelSim Wave Diagram Analysis

**Wave Diagram Requirements:**
- At least 15 clock cycles visible
- All signals displayed: clk, reset, enable (optional), seed, lfsr_out, random_bit
- Use Binary radix for lfsr_out for clarity
- Add marker/comment on 2-3 important transitions

**Submit your wave diagram screenshots (15 clock cycles):**

| Clock Cycle | Screenshot |
|-------------|------------|
| Reset           | ![image](https://hackmd.io/_uploads/Sk21M8fale.png)           |
| 1           | ![image](https://hackmd.io/_uploads/HkPGfLzpgg.png)           |
| 2           | ![image](https://hackmd.io/_uploads/BJL4GIMTll.png)           |
| 3           | ![image](https://hackmd.io/_uploads/BkNCMIGTxl.png)           |
| 4           | ![image](https://hackmd.io/_uploads/HJvJ7IzTex.png)           |
| 5           | ![image](https://hackmd.io/_uploads/HJabmLG6xl.png)           |
| 6           | ![image](https://hackmd.io/_uploads/rkDQm8Malx.png)           |
| 7           | ![image](https://hackmd.io/_uploads/S1cE7Ufall.png)           |
| 8           | ![image](https://hackmd.io/_uploads/B1qrXLfTxg.png)           |
| 9          | ![image](https://hackmd.io/_uploads/SycwQIMplg.png)           |
| 10          | ![image](https://hackmd.io/_uploads/rJGt7UGpxe.png)           |
| 11          | ![image](https://hackmd.io/_uploads/H1wq7Iz6gg.png)           |
| 12          | ![image](https://hackmd.io/_uploads/HJsjmIzaxe.png)           |
| 13          | ![image](https://hackmd.io/_uploads/SJi67UGTlx.png)           |
| 14          | ![image](https://hackmd.io/_uploads/SyL1NLf6xl.png)           |
| 15          | ![image](https://hackmd.io/_uploads/BJF_48fTxg.png)           |

### 3. Analysis Question - Zero Seed [10 points]

**Question:** Why can't the seed be `00000000`?

**Hint:** Try calculating feedback if all bits are 0. What happens in the next cycle?

**Your Answer:**
```
The result would repeat the '00000000' because of the foloowing process:

lfsr_reg = "00000000"
            ^ ^ ^ ^
            7 5 4 3  ← tapped bits

feedback = '0' xor '0' xor '0' xor '0' = '0'

when shifted:

temp = "00000000"

lfsr_reg <= temp;

this repeats for the entire run cycle.

```

### 4. Analysis Question - Sequence Length [10 points]

**Question:** From your wave diagram, does lfsr_out ever return to the seed value?

If yes, after how many clock cycles? If not visible in the wave, how many cycles are needed for an 8-bit LFSR with taps (7,5,4,3)?

**Hint:** With correct taps, an 8-bit LFSR will generate a maximum-length sequence = 2^8 - 1 = 255 states.

**Your Answer:**
```
When analyzed the 8-bit LFSR with taps (7,5,4,3) will form:
x^8 + x^6 + x^5 + x^4 + 1 polynomial. 

This is considered pritive polynomial and will cycle all
unique 255 states before repeating.

So the seed will only returned when reaching 255 cycles  with
all states exhausted.

```

---

## Task 2 Implementation Questions

### 1. Structural Implementation Code [10 points]

**Instructions:** Submit your complete structural implementation using D Flip-Flops and FOR GENERATE loop.

**Submit your `dff_enable.vhd` code here:**

```vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff_enable is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        enable : in std_logic;
        d : in std_logic;
        q : out std_logic);
end dff_enable;

architecture Behavioral of dff_enable is
    signal q_reg : std_logic := '0';
begin

    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                q_reg <= '0';
            elsif enable = '1' then
                q_reg <= d;
            end if;
        end if;
    end process;

    q <= q_reg;

end Behavioral;

```

**Submit your `lfsr_generator.vhd` code here:**

```vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lfsr_generator is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        enable : in std_logic;
        seed : in std_logic_vector(7 downto 0);
        lfsr_out : out std_logic_vector(7 downto 0));
end lfsr_generator;

architecture Structural of lfsr_generator is

    component dff_enable is
        Port (
            clk : in std_logic;
            reset : in std_logic;
            enable : in std_logic;
            d : in std_logic;
            q : out std_logic);
    end component;

    signal q_out : std_logic_vector(7 downto 0);
    signal dff_input : std_logic_vector(7 downto 0);
    signal feedback : std_logic;

begin

    feedback <= q_out(7) xor q_out(5) xor q_out(4) xor q_out(3);

    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                dff_input <= seed;
            else
                dff_input(7) <= feedback;
                dff_input(6) <= q_out(7);
                dff_input(5) <= q_out(6);
                dff_input(4) <= q_out(5);
                dff_input(3) <= q_out(4);
                dff_input(2) <= q_out(3);
                dff_input(1) <= q_out(2);
                dff_input(0) <= q_out(1);
            end if;
        end if;
    end process;

    gen_dff: for i in 0 to 7 generate
        dff_i: dff_enable
            port map (
                clk => clk,
                reset => reset,
                enable => enable,
                d => dff_input(i),
                q => q_out(i)
            );
    end generate;

    lfsr_out <= q_out;

end Structural;

```

### 2. Testbench for Structural Implementation [10 points]

**Instructions:** Create a testbench to test your `lfsr_generator` component. Use the same test scenarios as Task 1 to verify that both implementations produce identical results.

**Submit your testbench code for lfsr_generator here:**

```vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_lfsr_generator is
end tb_lfsr_generator;

architecture sim of tb_lfsr_generator is
    signal clk : std_logic := '0';
    signal reset : std_logic := '0';
    signal enable : std_logic := '0';
    signal seed : std_logic_vector(7 downto 0) := "10110100";
    signal lfsr_out : std_logic_vector(7 downto 0);

    constant T : time := 10 ns;
begin

    clk <= not clk after T / 2;

    uut: entity work.lfsr_generator
        port map (
            clk => clk,
            reset => reset,
            enable => enable,
            seed => seed,
            lfsr_out => lfsr_out);

    stim: process
    begin
        reset <= '1';
        enable <= '0';
        wait for T;

        reset <= '0';
        enable <= '1';
        wait for 15 * T;

        enable <= '0';
        wait for 5 * T;

        wait;
    end process;

end sim;

```

### ModelSim Wave Diagram Analysis (Task 2) [5 points]

**Requirements:** Results must be IDENTICAL to Task 1!

**Submit your wave diagram screenshots (15 clock cycles):**

| Clock Cycle | Screenshot |
|-------------|------------|
| Reset       | ![image](https://hackmd.io/_uploads/ryg_TyvG6le.png)           |
| 1           | ![image](https://hackmd.io/_uploads/rkDCywz6gg.png)           |
| 2           | ![image](https://hackmd.io/_uploads/ByKJgPzTgl.png)           |
| 3           | ![image](https://hackmd.io/_uploads/ry8xgDMTgx.png)           |
| 4           | ![image](https://hackmd.io/_uploads/B1bGlwfage.png)           |
| 5           | ![image](https://hackmd.io/_uploads/rJmXgwzpel.png)           |
| 6           | ![image](https://hackmd.io/_uploads/H10Exwzaxg.png)           |
| 7           | ![image](https://hackmd.io/_uploads/SyX7WwMpeg.png)           |
| 8           | ![image](https://hackmd.io/_uploads/SyMvePf6lx.png)           |
| 9           | ![image](https://hackmd.io/_uploads/HJ-_lvGagl.png)           |
| 10          | ![image](https://hackmd.io/_uploads/ryfYgPGaee.png)           |
| 11          | ![image](https://hackmd.io/_uploads/S1-qlvMTll.png)           |
| 12          | ![image](https://hackmd.io/_uploads/rymjlvG6gl.png)           |
| 13          | ![image](https://hackmd.io/_uploads/ryt6xwzagg.png)           |
| 14          | ![image](https://hackmd.io/_uploads/HyARgPzTle.png)           |
| 15          | ![image](https://hackmd.io/_uploads/SkWg-wzpgx.png)           |


### 3. Analysis Question - Loop Comparison [5 points]

**Question:** Explain the difference between:

**For loop (Task 1):** What is it used for? When is it executed?

**For generate loop (Task 2):** What is it used for? When is it executed?

**Your Answer:**
```
For loop (Task 1):
[Explain what for loop is used for and when it's executed]
The loop is used for:
1. To update the single signal lsfr_reg
2. To run shift logic using temp variable through slicing
3. Maintain changes to lsfr_reg state

This loop is executed during runtime for every raising edge.

For generate loop (Task 2):
[Explain what for generate loop is used for and when it's executed]
The loop is used for:
1. Generate 8 dff_enabled (D_flipflop) component
2. Assigning all the bit through dff_input() 
3. Maintaing all bit of q_out state 

This loop is executed before runtime to instantinate the all 
the generated dff_enabled componenet.

Key Differences:
[Explain the main differences between the two types of loops]
Key differences is the lsfr_general follow structural model and 
utilize the modular dff_enabled component. The lsfr_8bit is more 
on the debugging and simulation side, while lsfr_generator focused 
on synthesis and implementation. 

```

---

## Expected Results Reference

### Sample Calculation (for verification)

**Seed = `10110100`**

```
Clock 1 (Reset)
  lfsr_out = 10110100
  random_bit = 0

Clock 2 (Enable = 1)
  Calculate feedback:
    feedback = bit[7] XOR bit[5] XOR bit[4] XOR bit[3]
    feedback = 1 XOR 1 XOR 0 XOR 1 = 1
  
  Before shift: [1][0][1][1][0][1][0][0]
  After shift:  [1][1][0][1][1][0][1][0]
                 ^ feedback           ^ out
  
  lfsr_out = 11011010
  random_bit = 0

Clock 3 (Enable = 1)
  feedback = 1 XOR 0 XOR 1 XOR 1 = 1
  
  Before shift: [1][1][0][1][1][0][1][0]
  After shift:  [1][1][1][0][1][1][0][1]
  
  lfsr_out = 11101101
  random_bit = 1

Clock 4 (Enable = 1)
  feedback = 1 XOR 1 XOR 0 XOR 1 = 1
  
  lfsr_out = 11110110
  random_bit = 0
```