---
# System prepended metadata

title: Lab1
tags: [Study Journal, SOC Design]

---

# Lab1

## 1. Setting Environment
### Ubuntu on Virtualbox
- problem 1: add 250G disk on VM failed
solution:

- problem 2: internet doesn't work on VM
solution:

- problem 3: use ssh visit ubuntu on VM
solution: 

### Install Xilinx Vitis

## 2. Multiplication
### Vitis HLS
#### step1: C simulation
#### step2: C synthesye
#### step3: Co-simulation
During co-simulation the block-level control signal is needed, so the pragma "ap_ctrl_none" must be commend (also in csim and csyn).
```
//#pragma HLS INTERFACE ap_ctrl_none port=return
```
#### step4: Export RTL
Before export RTL, remember to remove the comment and synthesis again.
##### reference:
- [接口综合参考（Interface Synthesis Reference）](https://blog.csdn.net/weixin_42647783/article/details/102153098)

---
### Vivado
#### step1: Import HLS IP
#### step2: Block design
- ZYNQ PS
- Multiplication HLS IP
#### step3: Create HDL wrapper
#### step4: Generate bitstream

##### reference:
- [從零開始的 Xilinx SoC 開發（一）](https://ys-hayashi.me/2021/08/xilinx-soc-01/)
- [從零開始的 Xilinx SoC 開發（二）](https://ys-hayashi.me/2021/08/xilinx-soc-02/)
- [從零開始的 Xilinx SoC 開發（三）](https://ys-hayashi.me/2021/08/xilinx-soc-03/)
- [從零開始的 Xilinx SoC 開發（四）](https://ys-hayashi.me/2021/08/xilinx-soc-04/)
- [從零開始的 Xilinx SoC 開發（五）](https://ys-hayashi.me/2021/08/xilinx-soc-05/)

---
### Online FPGA (PYNQ)
#### Jupyter notebook remote
upload .hwh and .bit files
run python code
