**HW5 Non Pipelined CPU**
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**Objective**
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* Constructiong a Non pipelined cpu in behavioral verilog code

**Instruction**
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|Name | Opcode | Format | Description|
|-|-|-|-|
|NOP|0|NOP|Do nothing||
|BRA|1|BRA mem, cc|Jump according to condition codes|
|LOAD|2|LD reg, mem1|Load mem1 to reg|
|STORE|3|STR mem, src|Store src to mem|
|ADD|4|ADD reg, src|Add src to reg |
|SUB **(NEW)**|5|SUB reg, src|Sub src to reg |
|MULTIPLY|6|MUL reg, src|Multiply reg by src|
|COMPLEMENT|7|CMP reg, src|Not src and stored in reg|
|SHIFT|8|SHF reg, cnt|Cnt > 0, reg >> cnt ; Cnt < 0, reg << abs ( cnt )|
|ROTATE|9|ROT reg, cnt|Rotate according to cnt|
|AND **(NEW)**|10|AND reg, src| Reg && src |
|OR **(NEW)**|11|OR reg, src|Reg or Src |
|XOR **(NEW)**|12|XOR reg, src|Reg ^ src|
|HALT|13|HLT|Shut down|
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**Condition Code**
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|Condition|Short|Code|
|-|-|-|
|Always|ALW|0000|
|Carry|CCA|0001|
|Even|CCE|0010|
|Parity|CCP|0011|
|Zero|CCZ|0100|
|Negative|CCN|0101|
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**Instruction Format**
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|31 - 28 (4 bits)|27 - 24 (4 bits)|23 - 12 (4 bits) |11 - 0 (12 bits)|
|:-:|:-:|:-:|:-:|
|opcode|cc ; dst type ; src type|src address|dst address|

\* IR[27:24]: condition code

\* IR[27]: src type , 0 = reg (mem) ; 1 = imm

\* IR[26]: dst type , 0 = reg (mem) ; 1 = imm (Not Valid)

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