SPI
===

###### tags: `ASIC`

[TOC]

# SPI Pin



# Boot sequence:
1. ==HW Reset==
2. ==Power on sequence==
- Power on PD standby_top
- Release PD standby_top isolation cell
- Release clk_gen給PD standby_top的raw_rstn
- release arb_stdby clk (for power on from code persistent mode)
- release arb_stdby reset (for power on from code persistent mode)
- 設定arb_stdby (for power on from code persistent mode)
- release CPU sram pd
- 打開CPU clk
- Release CPU reset

3. ==AP透過command，將USPI_e切換到USPI_a==
4. CPU透過uspi_a fifo內的default machine code，讀進ICache，開始執行，CPU進入sleep mode
- (完成步驟2後，CPU會向aio_top發出0xff80_0000位置，aio_top會根據bootstrap pin將0xff80_0000轉址到對應的boot module)
- 打開USPI的interrupt mask
- 打開USPI interrupt到CPU的mask
- sleep指令
- 塞滿nop指令到64 bytes
5. !!AP開始傳mini boot code 給uspi_a!!，Interrupt起來喚醒CPU
6. CPU先將mini boot code前64byte讀進ICache，並執行，前64byte會開始lock下半段的mini boot code至ICache
7. CPU 在ICache開始執行mini boot code
- 設定PLL與clk_gen到適當工作頻率
- 設定bootstrap pin的inverse功能，選擇到boot from IROM mode
- enable OCRAM，Ocram Scan
- Receive leading packet
- Receive mainCode
- CheckSum compare
- Jump to mainCode

8. ==AP開始傳main code 給uspi_a==，uspi_a收到main code，並轉送到OCRAM

**Note:** 用==highlighted== 表示該步驟需由SW控制


- Leading Packet


- SK1 Boot Strap Pin


# Operation frequence
- Depend on OSC (oscillator) frequence
- if **OSC = 20 MHz**
- load miniBoot: **12 MHz**
- other stage: **50? MHz** (please refer to official spec)

# Boot from USPI Debug 記錄:
1. load完bit file後，先用AP讀寫0xfff6c074確定USPI_e是通的
2. 若不通，試著調高AP端電流，以S10P為例，0xffef02b4 : 0x0000403f
3. 調快或調慢clock，換短杜邦線，拿掉轉接座，以上為訊號的debug
4. USPI_e通了之後就可以開始從AP端送boot command
5. 可在mini boot code內埋log，先確保有進到mini boot code
6. 開始SW debug

Reference
===

[serial-peripheral-interface_串列(序列)週邊介面](https://goo.gl/nXnmE2)