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# System prepended metadata

title: libpmp article

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# libpmp article

## Abstract-Liu

## Introduction-Liu

##  RISC-V PMP Explained-Liu

In this section, we describe the hardware design of Physical Memory Protection (PMP). PMP units are designed to limit the physical addresses accessible by software running on a hart. They provides per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region. Since they are belonging to CSRs, we can only use privileged instruction like csrw and csrr to directly visit them. We only discuss PMP in RV32 since RV64 is very similar.


PMP entries are described by an 8-bit configuration registerand one MXLEN-bit (like 32 bits) address register. Each of them contains a PMP configuration register (pmpxcfg) and a PMP address register (pmpaddrx), managing the privilege of related memory. Up to 64 PMP entries are supported. All PMP CSR fields are WARL and they are only accessible to M-mode.

### 1. PMP configuration registers

The PMP configuration registers are densely packed into CSRs to minimize context-switch time. For RV32, sixteen CSRs, pmpcfg0–pmpcfg15, hold the configurations pmp0cfg–pmp63cfg for the 64 PMP entries (Fig. ??).  

<img src="tmp.assets/image-20221212010340987.png" alt="image-20221212010340987" style="zoom:50%;" />

Each PMP configuration register whose layout is showed in Figure ?? has R, W, X bits. When the three bits are set,  the PMP entry permits read, write, and instruction execution respectively. Attempting to do anything with a PMP region that does not have corresponding permissions will raise an exception. The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored. Locked PMP entries remain locked until the hart is reset. The remaining field, A, is described in the following sections. 

![image-20221212011044781](tmp.assets/image-20221212011044781.png)

### 2. PMP address registers

The PMP address registers are CSRs named pmpaddr0–pmpaddr63. Each PMP address register encodes bits 33–2 of a 34-bit physical address for RV32, as shown in Figure ??. Not all physical address bits may be implemented, and so the pmpaddr registers are **WARL**.

![image-20221212011523164](tmp.assets/image-20221212011523164.png)


### 3. Address Matching

The A field in a PMP entry’s configuration register encodes the address-matching mode of the associated PMP address register. Four modes are provided which are OFF, TOR, NA4 and NAPOT.  When A=0 (OFF mode), this PMP entry is disabled and matches no addresses. If A=1 which means TOR is selected, the associated address register forms the top of the address range and the preceding PMP address register forms the bottom of the address range. If PMP entry *i*’s A field is set to TOR, the entry matches any address *y* such that pmpaddr*i−1* *≤* *y <* pmpaddr*i* (irrespective of the value of pmpcfg*i−1* ). If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address *y <* pmpaddr0. We mainly use these two modes to implement our algorithm.



### 4. Priority and Matching Logic

PMP entries are statically prioritized. The lowest-numbered PMP entry that matches any byte of an access determines whether that access succeeds or fails. The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits.

If a PMP entry matches all bytes of an access, then the L, R, W, and X bits determine whether the access succeeds or fails. If the L bit is clear and the privilege mode of the access is M, the access succeeds. Otherwise, if the L bit is set or the privilege mode of the access is S or U, then the access succeeds only if the R, W, or X bit corresponding to the access type is set.

If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.






## Challenges of Utilizing RISC-V PMP-Xie
介绍RISC-V PMP使用的一些问题，主要是PMP entry有限。

目前，RV32 PMP 依赖于 32 位 CSR以存储PMP configuration registers，并且每个CSR可以存储4个8bits的PMP configuration registers。 RV32 PMP提供了16个CSR寄存器供PMP configuration registers存储，因此它最多支持 64 个pmp entries。开发人员有责任确保应用程序绝不会同时创建超过 64 个physical memory region的隔离请求。 这意味着开发人员必须在运行时检查活动physical memory region的数量，这些physical memory region由应用程序本身和它所依赖的第三方库使用。 否则，该程序可能无法正确受益于 PMP。 这个问题破坏了 PMP 的可用性，并阻碍了开发人员积极使用它。

使用大寄存器（例如 1024 位）不会扩展，因为 PMP 需要额外的存储空间来将configuration registers与memory region相关联。 例如，要支持 512 个隔离请求，每个configuration registers 需要8个位，该寄存器无法满足如此多的请求。除此之外，存储PMP address的CSR寄存器需要512个，该实现不符合实际。

## Software Abstraction of libpmp-Liu,Wang
介绍libpmp的实现方案。

## Evaluation-Li
介绍评估libpmp的方案和结果。
搞100，1000，10000，100000个隔离请求，测100次访问地址的平均时间，画图。
### Performance


## Related Work-Liu
介绍其他与PMP相关的工作。

## Discussion-Zhang
介绍一下后面还能做哪些工作。

## Conclusion-Zhang
总结做的所有工作

## Acknowledgment
致谢fw