# IC 封裝測試(VLSI)

### VLSI Design & Manufacturing Flow

### VLSI Development Flow

### Why Do Circuits Fail?
- Human design errors <- verify
- Manufacturing defects <- test
- Package defects <- test
- Filed(Environment) failures <- test
- Temperature,humidity,power,etc..

### Design Verification
- Performed at differnet levels of abstraction during design
- Simulation are used at various levels to test for
- Design errors in behavioral or RTL
- Design to meet timing/area/power requirements after synthesis

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### Testing
- Check the correctness of the manufactured circuit
- Detect and eliminate faulty circuits
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### Verification vs. Testing
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### Importance of Testing
- Moore's Law results from decreasing feature size
- From 10s of um to 10s of ns for transistors and interconnecting wires
- Operation frequencies have increased from 100KHZ to several GHz
- Decreasing feature size increases probability of defects during manufacturing porcess
- A single faulty tansistor or wire results in faulty IC
- Testing is required to guarantee fault-free products

- N: the number of transistors in a circuit(chip)
- p: the probability that a transistor is faulty
- Pf: the porbability that the chip is faulty
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- If p = 10^-6 and N = 10^6
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- The Rule of Ten: cost to detect faulty IC increases by an order of magnitude as we move from
- device -> PCB -> system -> field operation
- Testing is performed at all of these levels
- Testing is also used during
- Manufacturing to improve yield
- Diagnosis: failure mode analysis(FMA) to depict the faulty site
- Field operation to ensure fault-free system operation
- Initiate repair when faults are detected

### How to Do Testing?
- Testing typically consists of
- Apply test patterns T to inputs of circuit undder test (CUT)
- Analyze output responses R
- if correct(pass)，CUT is assumed to be fault-free
- if incorrect(fail)，CUT is faulty
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### Testing During VLSI Development
- Design verificaiton targets design errors
- Corrections are made prior to fabrication
- Remaining tests target manufacturing defects
- A defect is a physical imperfection that can lead to a fault
- Wafer Test (fabrication/die)
- Package Test/Final Test(packaged/chip)

### Electronic System Manufacturing
- A system consists of
- PCBs consisting of
- VLSI devices
- PCB fabrication is similar to VLSI fabrication
- Susceptible to defects
- Assembly steps are also susceptible to defect
- Testing is performed at all stages of manufacturing
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### Key Issues in Testing
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### Fault Models
- Describe the effects of physical faults
- Claim: high coverage against physical faults
- A given fault model has k types of faults
- k = 2 for most fault models
- A given circuit has n possible fault sites
- A good fault model is computationally efficiently for simulation and accurately reflects behavior of defects
- No single fault model works for all possible defects

### Multiple Fault Models
- A CUT can have multiple faults
- Number of multiple faults = (k+1)^n-1
- Each fault site can have 1-of-k fault types or be fault-free
- The "-1" represents the fault-free circuit
- Impractical for any but very small circuits

### Single Fault Models
- A CUT has only 1 fault
- Number of single faults = k x n
- Good single fault coverage generally implies good mutiple fault coverage

### Equivalent Faults
- One or more single faults taht have identical behavioral for all possible test patterns
- Only one fault from a set of equivalent faults needs to be simulated to determine whether these faults are detected by a given test pattern

### Fault Collapsing
- Remove equivalent faults
- Except for the representative one to be simulated
- Reduce the total number of faults under considered
- Reduce fault somulation time
- Reduce test pattern generation time

### Single Stuck-at Faults
- Only one single line is permanently stuck at 1 or 0
- #fault types = 2
- Example circuit:
- #fault sites = 9
- #single faults = 2x9 = 18
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### Fault Simulation
- Simulation
- Determine how a fault-free circuit should work
- Fault simulation
- Determine the behavior of a faulty circuit
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- Simulation under the input pattern {1,0,0,0} with fault E sa()

### Test Pattern
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