# Assignment1: RISC-V Assembly and Instruction Pipeline
github: contributed by <[austin779](https://github.com/austin779/ca2025-quizzes)>
>[!Note] AI tools usage
>I use ChatGPT to assist with Quiz 1 by providing code annotations
## The definition of RISC-V 32 registers list
- RV32I is a ISA with 32bit data bus and 32 registers
- in this assignment1,i used some of them to implement algorithm in assembly
1. return address register->x1 ,when calling a function ,the point counter will point to the address of calle function's first instruction
2.

## Problem B
### Overview
i use RV32I instruction set to implement the uf8 decoder and encoder
### uf8
| variable | C expression | functionality |
| ---------- | ---------------------------------- | ------------------ |
| `mantissa` | `fl & 0x0F` | 取低 4 位 |
| `exponent` | `fl >> 4` | 取高 4 位 |
| `offset` | `(0x7FFF >> (15 - exponent)) << 4` | 根據 exponent 算一個偏移值 |
| return | `(mantissa << exponent) + offset` | 回傳解碼結果 |
---
| rigister | context |
| ---- | --------------------------------------------- |
| `a0` | parameter fl（呼叫時傳入） |
| `t0` | mantissa |
| `t1` | exponent |
| `t2` | offset |
| `t3` | temporary：`15 - exponent` and `(mantissa << exponent)` |

q1_b_v1.s
execution result