---
# System prepended metadata

title: Lab8

---

Name : T. Venkat Kaushal
Roll Number: CS22B058

----
# Lab8
## Question 1

Verilog code:
1. Half Adder module:
```verilog=
module half_adder (
    input a,b,
    output sum,carry
);

assign sum = a ^ b;
assign carry = a & b;

endmodule
```
2. Full Adder module:
```verilog=
module full_adder(
    input a,b,cin,
    output sum,carry
);

wire c,c1,s;

half_adder ha0(a,b,s,c);
half_adder ha1(cin,s,sum,c1);

assign carry = c | c1 ;

endmodule
```

3. Testbench for Full Adder
```verilog=
module full_adder_tb;
reg a,b,cin;
wire sum,carry;

full_adder uut(a,b,cin,sum,carry);

initial begin
a = 0; b = 0; cin = 0;
#10
a = 0; b = 0; cin = 1;
#10
a = 0; b = 1; cin = 0;
#10
a = 0; b = 1; cin = 1;
#10
a = 1; b = 0; cin = 0;
#10
a = 1; b = 0; cin = 1;
#10
a = 1; b = 1; cin = 0;
#10
a = 1; b = 1; cin = 1;
#10
$finish();
end
                
endmodule
```

4. Timing Diagram:
[![Screenshot 2024-04-06 234832](https://hackmd.io/_uploads/SyxmzGklC.png)
](https://)

---
## Question 2

1. Need to have Full Adder module
2. 4 bit Ripple Carry Adder
```verilog=
module rippe_adder(X, Y, S, Co);
 input [3:0] X, Y;
 output [3:0] S;
 output Co;
 wire w1, w2, w3;
 fulladder u1(X[0], Y[0], 1'b0, S[0], w1);
 fulladder u2(X[1], Y[1], w1, S[1], w2);
 fulladder u3(X[2], Y[2], w2, S[2], w3);
 fulladder u4(X[3], Y[3], w3, S[3], Co);
endmodule
```

To verify: Testbench

```verilog=
module tb_RippleCarryAdder;
reg [3:0]a,b;
reg cin;
wire [3:0]sum;
wire c4;

RippleCarryAdder uut(a,b,cin,sum,c4);

initial begin
cin = 0;
a = 4'b0110;
b = 4'b1100;
#100
a = 4'b1110;
b = 4'b1000;
#100
a = 4'b0111;
b = 4'b1110;
#100
a = 4'b0010;
b = 4'b1001;
#100
$finish();
end
                
endmodule
```
![Screenshot 2024-04-07 012048](https://hackmd.io/_uploads/B14ADQJe0.png)

## Question 3

2x1 MUX
```verilog=
module MUX_2x1_gate_level (
    input wire A, B, S,
    output wire Y       
);

assign Y = (~S & A) | (S & B);

endmodule
```

Testbench

```verilog=
module tb_mux_2x1;
    reg A, B, S;
    wire Y;
    MUX_2x1_gate_level uut (
        .A(A),
        .B(B),
        .S(S),
        .Y(Y)
    );
    
    integer i,j,k;
    initial begin
        
        
    for (i = 0; i < 2; i = i + 1) begin
        for (j = 0; j < 2; j = j + 1) begin
            for (k = 0; k < 2; k = k + 1) begin
                A = i;
                B = j;
                S = k;
                #50;
            end
        end
    end
        
        
    $finish;
    end

endmodule
```
![Screenshot 2024-04-07 012954](https://hackmd.io/_uploads/HkpXqXyxR.png)


