---
# System prepended metadata

title: CO Lab 9

---

Computer Organization 9

Name: T.Venkat Kaushal
Roll Number: CS22B058

---
## Question 1
Verilog Code for ALU: 
This code supports ADD, SUB, AND, OR Operations

```verilog=
module ALU_2bit (
    input wire [1:0] A, B,
    input wire [1:0] Ctrl,
    output reg [1:0] Out
);
    
    always @(*) begin
        case (Ctrl)
            2'b00: Out = A + B;
            2'b01: Out = A - B;
            2'b10: Out = A & B;
            2'b11: Out = A | B;
        endcase
    end

endmodule
```

Testbench
```verilog=
module ALU_TestBench();

    reg [1:0] A, B;
    reg [1:0] Ctrl;
    
    wire [1:0] Out_ALU;
    
    ALU_2bit uut (
        .A(A),
        .B(B),
        .Ctrl(Ctrl),
        .Out(Out_ALU)
    );

    initial begin
        A = 2'b10;
        B = 2'b01;
        Ctrl = 2'b00;
        #100;
        
        A = 2'b10;
        B = 2'b01;
        Ctrl = 2'b01;
        #100;

        A = 2'b10;
        B = 2'b01;
        Ctrl = 2'b10;
        #100;

        A = 2'b10;
        B = 2'b01;
        Ctrl = 2'b11;
        #100;
        
        $finish;
    end

endmodule
```
![Screenshot 2024-04-07 014212](https://hackmd.io/_uploads/BJ0xp7ylA.png)

---
## Question 2

SimpleProcessor.v
```verilog=
module simple_processor (
    input [7:0] instruction,
    input [7:0] data_in,
    output reg [7:0] data_out
);

    reg [7:0] memory [255:0];
    reg [7:0] reg_file [15:0];

    reg [4:0] dest_reg;
    reg [3:0] offset;
    reg [1:0] src_reg;
    reg load;

 
    always @(*) begin
        load = instruction[7];
        dest_reg = instruction[6:5];
        offset = instruction[4:2];
        src_reg = instruction[1:0];
    end
    always @(*) begin
        if (load)
		begin 
            reg_file[dest_reg] = memory[reg_file[src_reg] + offset];
	    data_out = reg_file[dest_reg];
		end
        else 
		begin
	    reg_file[src_reg] = data_in;
            memory[reg_file[dest_reg] + offset] = reg_file[src_reg];
		end
    end
    initial begin
        reg_file[1] = 8'b00000001; // R1
        reg_file[2] = 8'b00000010; // R2

        
        memory[3] = 8'b11111111;
    end
```

Testbench
```verilog=
module simple_processor_tb;

    reg [7:0] instruction;
    reg [7:0] data_in;
    wire [7:0] data_out;

    // Instantiate the simple processor module
    simple_processor dut (
        .instruction(instruction),
        .data_in(data_in),
        .data_out(data_out)
    );

    
    initial begin
        // Load operation: lw R2, 3(R1)
        instruction = 8'b01001101; // Opcode: 0, Dest: 01 (R2), Offset: 011 (3), Src: 01 (R1)
        data_in = 8'b00000000; // Data input not used for load
        #100; // Wait for processing
        $display("Loaded value: %h", data_out);

        // Store operation: sw R2, 3(R1)
        instruction = 8'b11001101; // Opcode: 1, Dest: 01 (R2), Offset: 011 (3), Src: 01 (R1)
        data_in = 8'b10101010; // Data input to store
        #100; // Wait for processing
        
    end

endmodule
```
![Screenshot 2024-04-08 221903](https://hackmd.io/_uploads/ryBfli-eA.png)

---
## Question 3

### C Code:

```c=
#include<iostream>

int main ()
{
int sum = 0;
for(int i = 0; i < 100; i++){
sum = sum + i;
}
return 0;
}
```

Compiled the C++ code : g++ filename.cpp

Attached the pin to the executable of C program
```
../../../pin -t obj-intel64/inscount0.so -o CS22B058_lab9_q3.log -- /home/dsl4/a.out
```

Output:

```
Count 2166578
```
Screenshot:

![Screenshot from 2024-04-02 16-51-47](https://hackmd.io/_uploads/HyJv5Dtk0.png)