# W1 Computer Architecture review
professor:賴永康教授

:::success
course 1 - logic and computer design(review)
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>overview
* digital systems and computer science
* information representation
* number systems
* arithmetic operation
* base conservation
* decimal codes
* gray codes
* Alphanumeric codes

>>HW: design ripple carry binary adder with substactor

**Digital system**
>takes a set of discrete information **inputs** and discrete intenal information(system state)and generates a set of discrete information **outputs**


* types of Digital system
* no state present
* state present
* Synchronous ->透過clock
* Asynchronous
* signal
* an information variable represented by physical quality
* examples:
* digits 0,1
* False,True
* combinational circuits -> 給input會產出output
基本邏輯閘：NAND, NOR, Not gate
* examples:


註：利用NAND mapping可以節省電晶體使用，成本較低

* Verification : show that the final circuit designed implements the original spec
* basic Verification methods
* Manual Logic Analysis
find Truth table or Boolean equations
* Simulation

* Decoder
* Encoder
* Encoder priority
* multiplexer
* 2-to-1 multiplexer
* 4-to-1 multiplexer
* Half-Adder: two inputs(x,y) and two binary output(S,C)
//S: sum; C:carry
S=x'y+xy'
C=xy

* Full Adder: a combinational circuit that forms the arithmetic sum of three input bits; three input and two output
* input
* two significant bit to be added: x,y
* carry from previous lower significant position: z (carryin)
* output: 0-3
* C(carryout),S(sum)

* Binary Adder
* 4-bit Ripple-carry Binary Adder
* problem: delay time太長
* carry lookahead Adder
* improve ripple-carry binary adder delay time
* based on generate(產生)和propagate(傳遞)
* tradeoff: gate count 高

* Standard add-shift mutipliers

* Sequential circuits -> 有記憶性, need clock
e.g. control unit
contains:
* storage elements: Latches or Flip-Flops
* combinational logic

* D latch:存state value
* (negative)Edge-Triggered D Flip-Flop
* positive-edge Triggered D Flip-Flop

* State Diagram
* Mealy Model
* inputs, state
* x:input; y:output; 0,1:state
* Moore Model (記：慕斯,MOOre to the State)
* only State
* x:input, 2/1:output

* synchronous counters