# Gotcha 29: Sequential logic that requires blocking assignments

##　reference
Stuart Sutherland, Don Mills - Verilog and SystemVerilog Gotchas_ 101 Common Coding Errors and How to Avoid Them

## keynote

- RTL modeling guidelines

- RTL modeling guidelines recommend that nonblocking assignments should be used for modeling sequential assignments. In a zero-delay RTL model these guidelines help prevent simulation race conditions. A race condition occurs when a value is read at the same moment in time in which it is changing.

- non-RTL models

- These RTL coding guidelines are intended for modeling data flow and data manipulation. These RTL guidelines for using nonblocking assignments do not apply to non-RTL models.
- When the guidelines are applied to clock generators such as clock dividers and PLLs, the guidelines may actually cause race conditions in the generated clocks.
- [Question] what is non-RTL model?
- does clock dividers and PLLs is non-RTL model?

- Nonblocking assignments
- Nonblocking assignments represent the behavior of a flip-flop clock-to-Q delay, but with zero time.
- To do this, a nonblocking assignment breaks the assignment into two steps:
- first: evaluate the right-hand side expression,
- second: after a delta, update the left-hand side.
- During the delta, other statements scheduled for the current simulation time are executed.
- This two-step process is critical for preventing read/write race conditions in zero-delay RTL models.

- Blocking assignments
- Blocking assignments update the left-hand side immediately, without a clock-to Q delta.

## issue in gotcha 29
- code
- result

- The value of outl is being sampled at the sametime,and in the same delta, in whichthe value is being updated. Simulators are permitted to execute this in a read-then-write or a write-then-read event order. Gotcha!

## How to avoid this Gotcha

- To avoid this gotcha, it is necessary to code the clock divider so that out1 will always be evaluated before the delta in which outl will change. Thiscan be done a few ways, but perhaps the easiestis to use a blocking assignment for modeling the clock divider.




- Blocking assignments update the left-hand side immediately, without a clock-to Q delta. Using a blocking assignment will cause an immediate event on clk_divided2, which, if a positive edge, will immediately trigger the sensitivity list of the always @(elk_ divided2) block. Thus, the sampling of the right-hand side of out1 is guaranteed to occur before the delta in which out1 will change.