Caravel-soc_fpga simulation fail in vivado 2022.2 but pass in 2022.1 issue
# simulation result different in vivado 2022.1 and 2022.2
I file-in this issue and got reply in [xilinx forum](https://support.xilinx.com/s/question/0D54U00007H0dQgSAJ/simulation-result-different-in-vivado-20221-and-20222?language=en_US)
- reply from [xilinx forum](https://support.xilinx.com/s/question/0D54U00007H0dQgSAJ/simulation-result-different-in-vivado-20221-and-20222?language=en_US)
The code described in "Blocking Assignment" doesn't clearly define when the simulator does the processing and is implementation-dependent for the simulator.
Also, it's not surprising that the value differs from the expected value, since dumping the signals of the combinational circuit doesn't mean that the data is latched at the edge of the clock.
# code
[from caravel-soc_fpga by Josh for interrupt testbench in this commit](https://github.com/JoshSu0/caravel-soc_fpga/commit/53723087c587e10ae515099055481ed62a584654)
# error in 2022.2
- code no jump when interrupt occurs
# pass in 2022.1
- code jump when interrupt occurs
# 2022.2 stop at pc = 1000_06D4
```
100006c8: 00e7a023 sw a4,0(a5) # f0006000 <_etext+0xe00057f8>
100006cc: 260007b7 lui a5,0x26000
100006d0: 00100713 li a4,1
100006d4: 00e7a023 sw a4,0(a5) # 26000000 <_etext+0x15fff7f8>
100006d8: 00000013 nop
100006dc: 260007b7 lui a5,0x26000
100006e0: 0007a703 lw a4,0(a5) # 26000000 <_etext+0x15fff7f8>
100006e4: 00100793 li a5,1
100006e8: fef70ae3 beq a4,a5,100006dc <main+0x2ac>
```
```
reg_uart_enable = 1; //addr = f0006000
// Now, apply the configuration
reg_mprj_xfer = 1; //addr = 26000000
while (reg_mprj_xfer == 1);
```
[code link](https://github.com/JoshSu0/caravel-soc_fpga/blob/53723087c587e10ae515099055481ed62a584654/testbench/counter_la/counter_la.c#L104)
## correct behavior in 2022.1
```
always @(*) begin
next_state = 1'd0;
next_state = state;
case (state)
1'd1: begin
next_state = 1'd0;
end
default: begin
if ((mgmtsoc_wishbone_cyc & mgmtsoc_wishbone_stb)) begin
next_state = 1'd1;
end
end
endcase
end
```
[code link](https://github.com/JoshSu0/caravel-soc_fpga/blob/53723087c587e10ae515099055481ed62a584654/rtl/soc-efabless/mgmt_core.v#L4741C1-L4754C4)
## incorrect behavior in 2022.2
## patch solution
[link for commit](https://github.com/TonyHo722/caravel-soc_fpga/commit/7d6d21e660eca14712a153f17589d51477166392)
```
commit 7d6d21e660eca14712a153f17589d51477166392 (HEAD -> main)
Author: tonyho <TonyHo@via.com.tw>
Date: Sat Aug 19 23:44:43 2023 +0800
patch vivado 2022.2 simulation fail issue
diff --git a/rtl/soc-efabless/mgmt_core.v b/rtl/soc-efabless/mgmt_core.v
index 40b9cb9..d3e43d7 100644
--- a/rtl/soc-efabless/mgmt_core.v
+++ b/rtl/soc-efabless/mgmt_core.v
@@ -4739,7 +4739,7 @@ end
assign gpioin5_gpioin5_irq = (gpioin5_pending_status & gpioin5_enable_storage);
assign gpioin5_gpioin5_status = gpioin5_gpioin5_trigger;
always @(*) begin
- next_state = 1'd0;
+ //tony_debug next_state = 1'd0;^M
next_state = state;
case (state)
1'd1: begin
```
# root cause in vivado 2022.2
## dump next_state, the result is fail
[commit link](https://github.com/TonyHo722/caravel-soc_fpga/commit/1bee5cbcebc349ae430f3a96c642cd11be9759b7)
```
****** xsim v2022.2 (64-bit)
**** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
**** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source xsim.dir/counter_la_tb_elab/xsim_script.tcl
# xsim {counter_la_tb_elab} -autoloadwcfg -runall
Time resolution is 1 ps
run -all
Reading counter_la.hex
counter_la.hex loaded into memory
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13
0=> dump next_state=0
768338=> dump next_state=0
Monitor: Timeout, Test LA (RTL) Failed
```
# dump more in sensitivity list, the result is fail
[commit link](https://github.com/TonyHo722/caravel-soc_fpga/commit/633609dde31050c8e61f762970045318dae3bf6a)
```
****** xsim v2022.2 (64-bit)
**** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
**** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source xsim.dir/counter_la_tb_elab/xsim_script.tcl
# xsim {counter_la_tb_elab} -autoloadwcfg -runall
Time resolution is 1 ps
run -all
Reading counter_la.hex
counter_la.hex loaded into memory
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13
0=> dump state=0
0=> dump next_state=0
0=> dump mgmtsoc_wishbone_cyc=0
0=> dump mgmtsoc_wishbone_stb=x
0=> dump mgmtsoc_wishbone_cyc=x
13=> dump mgmtsoc_wishbone_cyc=0
13=> dump mgmtsoc_wishbone_stb=0
2188=> dump mgmtsoc_wishbone_stb=1
32213=> dump mgmtsoc_wishbone_stb=0
32413=> dump mgmtsoc_wishbone_stb=1
62438=> dump mgmtsoc_wishbone_stb=0
62838=> dump mgmtsoc_wishbone_stb=1
89238=> dump mgmtsoc_wishbone_stb=0
89688=> dump mgmtsoc_wishbone_stb=1
96613=> dump mgmtsoc_wishbone_stb=0
96713=> dump mgmtsoc_wishbone_stb=1
96763=> dump mgmtsoc_wishbone_stb=0
96788=> dump mgmtsoc_wishbone_stb=1
126813=> dump mgmtsoc_wishbone_stb=0
127113=> dump mgmtsoc_wishbone_stb=1
134038=> dump mgmtsoc_wishbone_stb=0
134138=> dump mgmtsoc_wishbone_stb=1
134188=> dump mgmtsoc_wishbone_stb=0
134613=> dump mgmtsoc_wishbone_stb=1
134663=> dump mgmtsoc_wishbone_stb=0
134688=> dump mgmtsoc_wishbone_stb=1
164713=> dump mgmtsoc_wishbone_stb=0
164888=> dump mgmtsoc_wishbone_stb=1
164938=> dump mgmtsoc_wishbone_stb=0
165588=> dump mgmtsoc_wishbone_stb=1
195613=> dump mgmtsoc_wishbone_stb=0
195888=> dump mgmtsoc_wishbone_stb=1
195938=> dump mgmtsoc_wishbone_stb=0
195963=> dump mgmtsoc_wishbone_stb=1
196013=> dump mgmtsoc_wishbone_stb=0
196038=> dump mgmtsoc_wishbone_stb=1
222438=> dump mgmtsoc_wishbone_stb=0
222988=> dump mgmtsoc_wishbone_stb=1
223238=> dump mgmtsoc_wishbone_stb=0
223263=> dump mgmtsoc_wishbone_stb=1
249663=> dump mgmtsoc_wishbone_stb=0
249938=> dump mgmtsoc_wishbone_stb=1
250188=> dump mgmtsoc_wishbone_stb=0
250338=> dump mgmtsoc_wishbone_stb=1
250588=> dump mgmtsoc_wishbone_stb=0
250613=> dump mgmtsoc_wishbone_stb=1
277013=> dump mgmtsoc_wishbone_stb=0
277438=> dump mgmtsoc_wishbone_stb=1
277688=> dump mgmtsoc_wishbone_stb=0
277738=> dump mgmtsoc_wishbone_stb=1
304138=> dump mgmtsoc_wishbone_stb=0
304288=> dump mgmtsoc_wishbone_stb=1
304538=> dump mgmtsoc_wishbone_stb=0
304688=> dump mgmtsoc_wishbone_stb=1
304938=> dump mgmtsoc_wishbone_stb=0
304963=> dump mgmtsoc_wishbone_stb=1
331363=> dump mgmtsoc_wishbone_stb=0
331763=> dump mgmtsoc_wishbone_stb=1
332013=> dump mgmtsoc_wishbone_stb=0
332163=> dump mgmtsoc_wishbone_stb=1
332413=> dump mgmtsoc_wishbone_stb=0
332438=> dump mgmtsoc_wishbone_stb=1
358838=> dump mgmtsoc_wishbone_stb=0
359388=> dump mgmtsoc_wishbone_stb=1
359638=> dump mgmtsoc_wishbone_stb=0
359663=> dump mgmtsoc_wishbone_stb=1
386063=> dump mgmtsoc_wishbone_stb=0
386338=> dump mgmtsoc_wishbone_stb=1
386588=> dump mgmtsoc_wishbone_stb=0
386738=> dump mgmtsoc_wishbone_stb=1
386988=> dump mgmtsoc_wishbone_stb=0
387013=> dump mgmtsoc_wishbone_stb=1
413413=> dump mgmtsoc_wishbone_stb=0
413838=> dump mgmtsoc_wishbone_stb=1
414088=> dump mgmtsoc_wishbone_stb=0
414138=> dump mgmtsoc_wishbone_stb=1
440538=> dump mgmtsoc_wishbone_stb=0
440688=> dump mgmtsoc_wishbone_stb=1
440938=> dump mgmtsoc_wishbone_stb=0
441088=> dump mgmtsoc_wishbone_stb=1
441338=> dump mgmtsoc_wishbone_stb=0
441363=> dump mgmtsoc_wishbone_stb=1
467763=> dump mgmtsoc_wishbone_stb=0
468163=> dump mgmtsoc_wishbone_stb=1
468413=> dump mgmtsoc_wishbone_stb=0
468563=> dump mgmtsoc_wishbone_stb=1
468813=> dump mgmtsoc_wishbone_stb=0
468838=> dump mgmtsoc_wishbone_stb=1
495238=> dump mgmtsoc_wishbone_stb=0
495788=> dump mgmtsoc_wishbone_stb=1
496038=> dump mgmtsoc_wishbone_stb=0
496063=> dump mgmtsoc_wishbone_stb=1
522463=> dump mgmtsoc_wishbone_stb=0
522738=> dump mgmtsoc_wishbone_stb=1
522988=> dump mgmtsoc_wishbone_stb=0
523138=> dump mgmtsoc_wishbone_stb=1
523388=> dump mgmtsoc_wishbone_stb=0
523413=> dump mgmtsoc_wishbone_stb=1
549813=> dump mgmtsoc_wishbone_stb=0
550238=> dump mgmtsoc_wishbone_stb=1
550488=> dump mgmtsoc_wishbone_stb=0
550538=> dump mgmtsoc_wishbone_stb=1
576938=> dump mgmtsoc_wishbone_stb=0
577088=> dump mgmtsoc_wishbone_stb=1
577338=> dump mgmtsoc_wishbone_stb=0
577488=> dump mgmtsoc_wishbone_stb=1
577738=> dump mgmtsoc_wishbone_stb=0
577763=> dump mgmtsoc_wishbone_stb=1
604163=> dump mgmtsoc_wishbone_stb=0
604563=> dump mgmtsoc_wishbone_stb=1
604813=> dump mgmtsoc_wishbone_stb=0
604963=> dump mgmtsoc_wishbone_stb=1
605213=> dump mgmtsoc_wishbone_stb=0
605238=> dump mgmtsoc_wishbone_stb=1
631638=> dump mgmtsoc_wishbone_stb=0
632188=> dump mgmtsoc_wishbone_stb=1
632438=> dump mgmtsoc_wishbone_stb=0
632463=> dump mgmtsoc_wishbone_stb=1
658863=> dump mgmtsoc_wishbone_stb=0
659138=> dump mgmtsoc_wishbone_stb=1
659388=> dump mgmtsoc_wishbone_stb=0
659538=> dump mgmtsoc_wishbone_stb=1
659788=> dump mgmtsoc_wishbone_stb=0
659813=> dump mgmtsoc_wishbone_stb=1
686213=> dump mgmtsoc_wishbone_stb=0
686638=> dump mgmtsoc_wishbone_stb=1
686888=> dump mgmtsoc_wishbone_stb=0
686938=> dump mgmtsoc_wishbone_stb=1
713338=> dump mgmtsoc_wishbone_stb=0
713488=> dump mgmtsoc_wishbone_stb=1
713738=> dump mgmtsoc_wishbone_stb=0
713888=> dump mgmtsoc_wishbone_stb=1
714138=> dump mgmtsoc_wishbone_stb=0
714163=> dump mgmtsoc_wishbone_stb=1
740563=> dump mgmtsoc_wishbone_stb=0
740963=> dump mgmtsoc_wishbone_stb=1
741213=> dump mgmtsoc_wishbone_stb=0
741363=> dump mgmtsoc_wishbone_stb=1
741613=> dump mgmtsoc_wishbone_stb=0
741638=> dump mgmtsoc_wishbone_stb=1
768038=> dump mgmtsoc_wishbone_stb=0
768338=> dump mgmtsoc_wishbone_stb=1
768338=> dump mgmtsoc_wishbone_cyc=1
768338=> dump next_state=0
Monitor: Timeout, Test LA (RTL) Failed
```
# SystemVerilog in xvlog do not execution always @(*) when t = 0
[commit link](https://github.com/TonyHo722/xvlog_2022.2/commit/24bc99c67dea50336b896bd3e7a23db151d055d2)
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