# Non-synthesizable Verilog Constructs
- synthesizable Verilog constructs for RTL design
- non-synthesizable constructs for testbench
## 15.1 Intra-delay and Inter-delay Assignments

### 15.1.1 Simulation for Blocking Assignments

reg clk;
reg [7:0] a,b,c,d;
always #10 clk = ~clk;
initial
begin
    clk=0;
    a=8'h2;
    b=8'h3;
    c=8'h4;
    d=8'h5;
end

always@(posedge clk)
begin
    a=b+c;
    b=a+d;
    c=a+b;
end


### 15.1.2 Simulation of Non-blocking Assignments

always@(posedge clk)
begin
    a<=b+c;
    b<=a+d;
    c<=a+b;
end


- [Question] what is wait construct?

## 15.2 The always and initial Procedural Block
- always procedural block to code the RTL design.
- The initial procedural block is used in the testbenches to generate stimulus at various time stamp.

### 15.2.1 Blocking Assignments with Inter-assignment Delays
- it delays both the evaluation of the assignment and update of the assignment

initial
begin
    clk =0;
    a=4;
    b=3;
    c=2;
    d=5;
end

always@(posedge clk)
begin
    b=a+a;
    #3 c=b+a;
    #1 d=c+a;
end


### 15.2.2 Blocking Assignments with Intra-assignment Delays

原文如下，紅色應該是寫錯的

修改如下
- In the intra-assignment delays with the blocking assignment, it delays the update of the assignment but not the evaluation of the assignment.

reference https://www.vlsifacts.com/delay-assignment-verilog/


always@(posedge clk)
begin
    b=a+a;
    c= #3 b+a;
    d= #1 c+a;
end

這個例子選的不好，看不出來 block assignment 的情況下，inter-delay 與 intra-delay有何不同。


### 15.2.3 Non-blocking Assignments with Inter-assignment Delays

- Using the inter-assignment delays with the non-blocking assignment, it delays both the evaluation of the assignment and the update of the assignment.

initial
begin
    clk =0;
    a=4;
    b=3;
    c=2;
    d=5;
#25
    a=4;
    b=3;
    c=2;
    d=5;
end

always@(posedge clk)
begin
    b <= a+a;
    #3 c <= b+a;
    #1 d <= c+a;
end


### 15.2.4 Non-blocking Assignments with Intra-assignment Delays
原文如下，紅色應該是寫錯的
修改如下
- In the intra-assignment delays with the non-blocking assignment, it delays the update of the assignment but not the evaluation of the assignment.

always@(posedge clk)
begin
    b <= a+a;
    c <= #3 b+a;
    d <= #1 c+a;
end