---
# System prepended metadata

title: make user_proj_example issue in AS code and irq port
tags: [caravel-lab]

---


# 20231005 status summary 
- AA code cause make user_proj_example fail issue in [STEP 1] - Running Synthesis
	- fixed by update AA code
- AS code cause make user_proj_example fail issue in [STEP 14] - Running Detailed Placement
	- hurry is debugging it
- irq port cause make user_proj_example fail issue in [STEP 36] - Running OpenROAD Antenna Rule Checker
	- root casue is confirmed

# AA code cause make user_proj_example fail issue in [STEP 1] - Running Synthesis

## 1003-hls05-01 - make user_proj_example fail [caused by tony's workaround AA code]

### reproduce this issue in below
- branch: 1003_merge_verify_rtl_hls05_repo

- terminal: u5 w1-alt7
```
tonyho@HLS05:~/workspace/fsic/caravel-lab/bash_auto/hls05$ nohup ./run_la_test1 2>&1 | tee run_la_test1.log &
```
- base this commit and run test: 
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/01eade114a68b6f8ffb01cd8d96da81da5a9a73c)
		- AS : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/18a6f51f3bf2fff27f7b743442fc43deb8b672a9)
		- AA : tony's workaround AA code

- result
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/4c39e7683bceb094113b3d3d2f017822432c7a4b)


```
[STEP 1]
[INFO]: Running Synthesis (log: ../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/runs/23_10_03_21_38/logs/synthesis/1-synthesis.log)...
[ERROR]: during executing yosys script /openlane/scripts/yosys/synth.tcl
[ERROR]: Log: ../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/runs/23_10_03_21_38/logs/synthesis/1-synthesis.log
[ERROR]: Last 10 lines:
No latch inferred for signal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_grant' from process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048'.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_grant [0]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_grant [1]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_grant [2]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
No latch inferred for signal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant' from process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048'.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant [0]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant [1]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant [2]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
No latch inferred ERROR: No latch inferred for signal `\axi_ctrl_logic.\next_trans' from always_latch process `\axi_ctrl_logic.$proc$/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/axi_ctrl_logic.sv:0$161'.
child process exited abnormally
```

## 1003-hls05-02 - make user_proj_example fail [caused by AS code]
- action 
	- update AA code

### reproduce this issue in below
- branch: 1003_merge_verify_rtl_hls05_repo

- terminal: u5 w1-alt7
```
tonyho@HLS05:~/workspace/fsic/caravel-lab/bash_auto/hls05$ nohup ./run_la_test1 2>&1 | tee run_la_test1.log &
```
- base this commit and run test: 
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/f03538164d238eaeb32fabe5e014f12bfd901791)
		- AS : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/18a6f51f3bf2fff27f7b743442fc43deb8b672a9)
		- AA : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/cbf29183f077afd46cba9230574c54cff6ebb510)

- result
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/961f6cd11fb28cfc9ec68dd848e04b9e952b84a5)


```
[STEP 14]
[INFO]: Running Detailed Placement (log: ../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_2/caravel_user_project/openlane/user_proj_example/runs/23_10_04_15_14/logs/routing/14-diode_legalization.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/dpl.tcl
[ERROR]: Log: ../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_2/caravel_user_project/openlane/user_proj_example/runs/23_10_04_15_14/logs/routing/14-diode_legalization.log
[ERROR]: Last 10 lines:
[INFO DPL-0035]  ANTENNA__06632__B2
[INFO DPL-0035]  ANTENNA__06632__B2
[INFO DPL-0035]  ANTENNA_input42_A
[INFO DPL-0035]  ANTENNA_input42_A
[INFO DPL-0035]  ANTENNA__13019__A
[INFO DPL-0035]  ANTENNA__13016__A
[INFO DPL-0035]  ANTENNA_input47_A
[ERROR DPL-0036] Detailed placement failed.
Error: dpl.tcl, 20 DPL-0036
child process exited abnormally

[ERROR]: Creating issue reproducible...
```

- comment
	- after update AA code then improve it, but still fail in AS code - detail check in below
	

# AS code cause make user_proj_example fail issue in [STEP 14] - Running Detailed Placement

## 1005-hls05-01 - make user_proj_example fail [caused by AS code]

### reproduce this issue in below
- branch: 1003_merge_verify_rtl_hls05_repo

- terminal: u5 w1-alt7
```
tonyho@HLS05:~/workspace/fsic/caravel-lab/bash_auto/hls05$ nohup ./run_la_test1 2>&1 | tee run_la_test1.log &
```
- base this commit and run: 
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/f03538164d238eaeb32fabe5e014f12bfd901791)
		- AS : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/18a6f51f3bf2fff27f7b743442fc43deb8b672a9)
		- AA : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/cbf29183f077afd46cba9230574c54cff6ebb510)

- result
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/961f6cd11fb28cfc9ec68dd848e04b9e952b84a5)

```
    update fail log - hls05/run_fsic.log - after sync axi_ctrl_logic.sv from fsic_fpga detail error log in below
    
    [STEP 14]
    [INFO]: Running Detailed Placement (log: ../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_2/caravel_user_project/openlane/user_proj_example/runs/23_10_04_15_14/logs/routing/14-diode_legalization.log)...
    [ERROR]: during executing openroad script /openlane/scripts/openroad/dpl.tcl
    [ERROR]: Log: ../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_2/caravel_user_project/openlane/user_proj_example/runs/23_10_04_15_14/logs/routing/14-diode_legalization.log
    [ERROR]: Last 10 lines:
    [INFO DPL-0035]  ANTENNA__06632__B2
    [INFO DPL-0035]  ANTENNA__06632__B2
    [INFO DPL-0035]  ANTENNA_input42_A
    [INFO DPL-0035]  ANTENNA_input42_A
    [INFO DPL-0035]  ANTENNA__13019__A
    [INFO DPL-0035]  ANTENNA__13016__A
    [INFO DPL-0035]  ANTENNA_input47_A
    [ERROR DPL-0036] Detailed placement failed.
    Error: dpl.tcl, 20 DPL-0036
    child process exited abnormally
```


## 1005-hls05-02 - make user_proj_example fail [irq issue]
- after use sw_caravel.v.patch then fixed [STEP 14] - Running Detailed Placement
	- but fail in  [STEP 36] - Running OpenROAD Antenna Rule Checker

### reproduce this issue in below
- branch: 1003_merge_verify_rtl_hls05_repo

- terminal: u5 w1-alt7
```
tonyho@HLS05:~/workspace/fsic/caravel-lab/bash_auto/hls05$ nohup ./run_la_test1 2>&1 | tee run_la_test1.log &
```
- base this commit and run: 
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/0aa344625f4d0c29a1444286ef917e86c7ad3820)
		- AS : use sw_caravel.v.patch to 
		- AA : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/cbf29183f077afd46cba9230574c54cff6ebb510)
		- MF=/home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3

- result
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/807ed2099593126784ace9f23e69368d002b011e)

```
    update fail log hls05/un_fsic.log - roll abck to sw_caravel.v.patch - exit after make user_proj_example
    - make user_proj_example error log detal in below
    
    [STEP 36]
    [INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/logs/signoff/36-antenna.log)...
    [INFO]: Saving current set of views in '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/results/final'...
    [INFO]: Saving current set of views in '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project'...
    [INFO]: Saving runtime environment...
    [INFO]: Generating final set of reports...
    [INFO]: Created manufacturability report at '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/reports/manufacturability.rpt'.
    [INFO]: Created metrics report at '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/reports/metrics.csv'.
    [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/reports/signoff/26-rcx_sta.slew.rpt'.
    [ERROR]: There are hold violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/reports/signoff/26-rcx_sta.min.rpt'.
    [INFO]: Saving current set of views in '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/results/final'...
    [INFO]: Generating final set of reports...
    [INFO]: Created manufacturability report at '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/reports/manufacturability.rpt'.
    [INFO]: Created metrics report at '../home/tonyho/workspace/debug/1003_merge_verify_rtl_hls05_repo_3/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_10/reports/metrics.csv'.
    [INFO]: Saving runtime environment...
    [ERROR]: Flow failed.

```

# irq port cause make user_proj_example fail issue in [STEP 36] - Running OpenROAD Antenna Rule Checker

- use a good code base to compare why 1005-u5-02 failed?
	- good code base in 1005-u5-01
	- fail code base in 1005-u5-02

## 1005-u5-01 - make verify-system_test111-gl [PASS]
### reproduce in below

- branch: 1005_AA_gl_issue

- terminal: u5 w1-alt1

- base this commit and run: 
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/846c56ac21653e833e1c6e83ac2e54660d326dfb)
		- AS : use sw_caravel.v.patch
		- AA : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/cbf29183f077afd46cba9230574c54cff6ebb510)
		- export MF=/ADATA2T/debug/fsic_1005_AA_gl_issue
- result
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/1ed785fb0e619a0616ac3c3eaeebd60a2d065b79)

```
update pass log ubuntu5/un_fsic.log - update AA module no error - exit after verify-system_test111-gl

```

## 1005-u5-02 - make user_proj_example fail [why fail fail?]
- 1005-u5-02 is come freom 1005-hls05-02
### reproduce this issue in below
- branch: 1005_merge_verify_rtl

- terminal: u5 w1-alt1

- base this commit and run: 
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/86b29ae55e90137f747458c5e3669e097b392260)
		- AS : use sw_caravel.v.patch 
		- AA : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/cbf29183f077afd46cba9230574c54cff6ebb510)
		- export MF=/ADATA2T/debug/fsic_1005_merge_verify_rtl

- result
	- [commit](https://github.com/TonyHo722/caravel-lab/commit/5b37df72dcac7a2d61ad1b22091df3583f482968)

```
    update fail log ubuntu5/run_fsic.log - double check the result with branch: 1003_merge_verify_rtl_hls05_repo, commit:807ed2099593126784ace9f23e69368d002b011e
    - make user_proj_example error log detal in below
    
    [STEP 36]
    [INFO]: Running OpenROAD Antenna Rule Checker (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/logs/signoff/36-antenna.log)...
    [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/results/final'...
    [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project'...
    [INFO]: Saving runtime environment...
    [INFO]: Generating final set of reports...
    [INFO]: Created manufacturability report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/reports/manufacturability.rpt'.
    [INFO]: Created metrics report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/reports/metrics.csv'.
    [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/reports/signoff/26-rcx_sta.slew.rpt'.
    [ERROR]: There are hold violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/reports/signoff/26-rcx_sta.min.rpt'.
    [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/results/final'...
    [INFO]: Generating final set of reports...
    [INFO]: Created manufacturability report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/reports/manufacturability.rpt'.
    [INFO]: Created metrics report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_05_14_44/reports/metrics.csv'.
    [INFO]: Saving runtime environment...
    [ERROR]: Flow failed.
```


- question
	- why  1005-u5-01 pass but 1005-u5-02 failed?
		- check the different part
			- PASS : /ADATA2T/debug/fsic_1005_AA_gl_issu
			- fail : /ADATA2T/debug/fsic_1005_merge_verify_rtl
				- copy fail log to a folder for future use
					- cp -r /ADATA2T/debug/fsic_1005_merge_verify_rtl /ADATA2T/debug/fsic_1005_merge_verify_rtl_fail_save
			- meld /ADATA2T/debug/fsic_1005_AA_gl_issue /ADATA2T/debug/fsic_1005_merge_verify_rtl
				- pin_order.cfg
				- user_proj_example.v
				- user_project_wrapper.v
		- both use the same code
			- AS : use sw_caravel.v.patch
			- AA : fsic_fpga [commit](https://github.com/bol-edu/fsic_fpga/commit/cbf29183f077afd46cba9230574c54cff6ebb510)

- action
	- copy file from pass to fail folder
		- pin_order.cfg
		- user_proj_example.v
		- user_project_wrapper.v
	- update source_fsic file to fail folder
	- run below command in fail folder
		- make -d user_proj_example 2>&1 | tee $LF/mpw-8c-user_proj_example.log
	- result is pass.
		- root cause is irq pin?
			- yes, after use from user_irq to irq port then pass
				- updat code in this [commit](https://github.com/TonyHo722/caravel-lab/commit/b61bef3918097886cf1a05facfa963e2f4ed9f62)


# question why default_nettype setting below
- in user_proj_example.v and user_project_wrapper.v
```
`default_nettype none
...
`default_nettype wire
```

## default_nettype setting do not cause issue, study it
- compare pass and working after change to from user_irq to irq
	- meld /ADATA2T/debug/fsic_1005_AA_gl_issue/caravel-lab ~/workspace/fsic/caravel-lab
		- user_proj_example.v
			- default_nettype setting?
		- user_project_wrapper.v
			- default_nettype setting?

![](https://hackmd.io/_uploads/H1rIqk2xT.png)

![](https://hackmd.io/_uploads/Byfnqk3lT.png)

