fsic_asic interrupt simulation fail gating by mgmt_protect module issue
# interrupt simulation issue in fsic_asic
I reference [caravel-soc_fpga](https://github.com/JoshSu0/caravel-soc_fpga/commit/6bd7bc104549fe93afa21cccf0608b9b171e3452) to porting interrupt reltaive code to [fsic_asic](https://github.com/bol-edu/fsic_asic). But the simulation failed. user logic generate interrupt but CPU do not jump to interrupt handler.
## Normal waveform from caravel-soc_fpga
[commit link](https://github.com/TonyHo722/caravel-soc_fpga/commit/2431d65cf00e33744b27d99a1627080f75fe9919)
## Bad waveform from fsic_asic
- In fsic_asic, gpioin0_gpioin0_pending keep 0 when irq asserted
- when user_irq[0]=1 then gpioin0_gpioin0_pending should be 1, but it is 0 in waveform.
[commit link](https://github.com/bol-edu/fsic_asic/commit/b86016ca67cb7964fe45d7c8df39e5771e7aac74)
# root cause
- [caravel-soc_fpga](https://github.com/TonyHo722/caravel-soc_fpga/commit/6bd7bc104549fe93afa21cccf0608b9b171e3452) remove mgmt_protect module, no need to set user_irq_enable=1.
- [fsic_asic](https://github.com/bol-edu/fsic_asic) include mgmt_protect module which come from [caravel](https://github.com/efabless/caravel/blob/main/verilog/rtl/caravel.v), we need to set user_irq_enable=1.
In fsic_asic, the [user_irq](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/user_project_wrapper.v#L77C18-L77C26) from user poject is gating by [user_irq_gates](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_protect.v#L181) in mgmt_protect module
I used the firmware code from caravel-soc_fpga need set [user_irq_enable](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_protect.v#L181)=1.
the user_irq_enable is connect to control register in [user_irq_ena_storage[2:0]](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L7851C1-L7860C5) (address = 0xF000_9800)
```
//set user_irq_ena for user_irq[0]
value = 1;
user_irq_ena_out_write(value);
```
[reference code](https://github.com/bol-edu/fsic_asic/commit/9d5011ebec628f9ae6cf8871e29dce24189249cc)
[USER_IRQ_ENA Document](https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/generated/user_irq_ena.html)
## reference code link in fsic_asic for mgmt_protect module in caravel.v
```
module caravel (
...
mgmt_protect mgmt_buffers (
...
);
...
endmodule
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/caravel.v#L600)
## reference code link in caravel-soc_fpga
```
// FPGA : Remove mgmt_protect module, passthrough
```
[code link](https://github.com/TonyHo722/caravel-soc_fpga/blob/josh/rtl/soc/caravel.v#L582C1-L582C50)
# how to run it?
1. base on this [commit](https://github.com/bol-edu/fsic_fpga/commit/ee68971af747e6a1e80e93aef51b1092b2d98e30) in fsic_fpga
2. base on this [commit](https://github.com/bol-edu/fsic_asic/commit/0a830ea2692b51667eb5b11a8b0f8688b7675e89) in fsic_asic
3. run xsim system in fsic_asic
```
(base) tonyho@ubuntu5:~/workspace/fsic/fsic_asic/verif/vsim/rsim$ ./run_xsim system
~/workspace/fsic/fsic_asic/verif/vsim/rsim ~/workspace/fsic/fsic_asic/verif/vsim/rsim
/home/tonyho/workspace/fsic/fsic_asic/src
dos2unix: converting file ../../fsic_fpga/rtl/user/rtl/rtl.f to Unix format...
dos2unix: converting file ../axilite_axis/rtl/rtl.f to Unix format...
dos2unix: converting file ../axis_switch/rtl/rtl.f to Unix format...
dos2unix: converting file ../config_ctrl/rtl/rtl.f to Unix format...
dos2unix: converting file ../fsic_clkrst/rtl/rtl.f to Unix format...
dos2unix: converting file ../io_serdes/rtl/rtl.f to Unix format...
dos2unix: converting file ../logic_analyzer/rtl/rtl.f to Unix format...
dos2unix: converting file ../mprj_io/rtl/rtl.f to Unix format...
Release Date: 08 24
~/workspace/fsic/fsic_asic/verif/vsim/rsim
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/tbuart.v" into library work
INFO: [VRFC 10-311] analyzing module tbuart
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/spiflash.v" into library work
INFO: [VRFC 10-311] analyzing module spiflash
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/fpga.v" into library work
INFO: [VRFC 10-311] analyzing module fpga
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/fsic_clock.v" into library work
INFO: [VRFC 10-311] analyzing module fsic_clock_div
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/macro/RAM128.pwr.v" into library work
INFO: [VRFC 10-311] analyzing module RAM128
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/macro/RAM256.v" into library work
INFO: [VRFC 10-311] analyzing module RAM256
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/project_define.svh" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/defines.v" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/user_defines.v" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_master.sv" into library work
INFO: [VRFC 10-311] analyzing module axilite_master
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_slave.sv" into library work
INFO: [VRFC 10-311] analyzing module axilite_slave
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axis_master.sv" into library work
INFO: [VRFC 10-311] analyzing module axi_fifo
INFO: [VRFC 10-311] analyzing module axis_master
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axis_slave.sv" into library work
INFO: [VRFC 10-311] analyzing module axis_slave
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axi_ctrl_logic.sv" into library work
INFO: [VRFC 10-311] analyzing module axi_ctrl_logic
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axil_axis.sv" into library work
INFO: [VRFC 10-311] analyzing module AXIL_AXIS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axis_switch.v" into library work
INFO: [VRFC 10-311] analyzing module AXIS_SW
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/config_ctrl.v" into library work
INFO: [VRFC 10-311] analyzing module CFG_CTRL
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/fsic_clkrst.v" into library work
INFO: [VRFC 10-311] analyzing module FSIC_CLKRST
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/io_serdes.v" into library work
INFO: [VRFC 10-311] analyzing module IO_SERDES
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/fsic_coreclk_phase_cnt.v" into library work
INFO: [VRFC 10-311] analyzing module fsic_coreclk_phase_cnt
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/fsic_io_serdes_rx.v" into library work
INFO: [VRFC 10-311] analyzing module fsic_io_serdes_rx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/logic_anlz.dummy_io.vd" into library work
INFO: [VRFC 10-311] analyzing module LOGIC_ANLZ
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mprj_io.sv" into library work
INFO: [VRFC 10-311] analyzing module MPRJ_IO
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/user_subsys.all.v" into library work
INFO: [VRFC 10-311] analyzing module AXIL_SLAV
INFO: [VRFC 10-311] analyzing module AXIS_MSTR
INFO: [VRFC 10-311] analyzing module AXIS_SLAV
INFO: [VRFC 10-311] analyzing module IRQ_MUX
INFO: [VRFC 10-311] analyzing module LA_MUX
INFO: [VRFC 10-311] analyzing module USER_PRJ
INFO: [VRFC 10-311] analyzing module USER_SUBSYS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/fsic.vo" into library work
INFO: [VRFC 10-311] analyzing module FSIC
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/user_project_wrapper.v" into library work
INFO: [VRFC 10-311] analyzing module user_project_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/housekeeping_spi.v" into library work
INFO: [VRFC 10-311] analyzing module housekeeping_spi
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/housekeeping.wire.v" into library work
INFO: [VRFC 10-311] analyzing module housekeeping
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mgmt_protect_hv.wire.v" into library work
INFO: [VRFC 10-311] analyzing module mgmt_protect_hv
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mgmt_protect.wire.v" into library work
INFO: [VRFC 10-311] analyzing module mgmt_protect
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/clock_div.wire.v" into library work
INFO: [VRFC 10-311] analyzing module clock_div
INFO: [VRFC 10-311] analyzing module odd
INFO: [VRFC 10-311] analyzing module even
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/caravel_clocking.wire.v" into library work
INFO: [VRFC 10-311] analyzing module caravel_clocking
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/buff_flash_clkrst.wire.v" into library work
INFO: [VRFC 10-311] analyzing module buff_flash_clkrst
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/ring_osc2x13.v" into library work
INFO: [VRFC 10-311] analyzing module delay_stage
INFO: [VRFC 10-311] analyzing module start_stage
INFO: [VRFC 10-311] analyzing module ring_osc2x13
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/digital_pll_controller.v" into library work
INFO: [VRFC 10-311] analyzing module digital_pll_controller
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/digital_pll.wire.v" into library work
INFO: [VRFC 10-311] analyzing module digital_pll
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/gpio_logic_high.wire.v" into library work
INFO: [VRFC 10-311] analyzing module gpio_logic_high
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/gpio_signal_buffering.wire.v" into library work
INFO: [VRFC 10-311] analyzing module gpio_signal_buffering
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/VexRiscv_MinDebug.v" into library work
INFO: [VRFC 10-311] analyzing module VexRiscv
INFO: [VRFC 10-311] analyzing module StreamFifoLowLatency
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mprj_logic_high.wire.v" into library work
INFO: [VRFC 10-311] analyzing module mprj_logic_high
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mprj2_logic_high.wire.v" into library work
INFO: [VRFC 10-311] analyzing module mprj2_logic_high
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mgmt_core.patrick.v" into library work
INFO: [VRFC 10-311] analyzing module mgmt_core
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mgmt_core_wrapper.wire.v" into library work
INFO: [VRFC 10-311] analyzing module mgmt_core_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/pads.wire.v" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mprj_io_buffer.wire.v" into library work
INFO: [VRFC 10-311] analyzing module mprj_io_buffer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/mprj_io.wire.v" into library work
INFO: [VRFC 10-311] analyzing module mprj_io
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/chip_io.wire.v" into library work
INFO: [VRFC 10-311] analyzing module chip_io
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/gpio_defaults_block.wire.v" into library work
INFO: [VRFC 10-311] analyzing module gpio_defaults_block
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/gpio_control_block.wire.v" into library work
INFO: [VRFC 10-311] analyzing module gpio_control_block
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/constant_block.wire.v" into library work
INFO: [VRFC 10-311] analyzing module constant_block
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/user_id_programming.wire.v" into library work
INFO: [VRFC 10-311] analyzing module user_id_programming
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/simple_por.wire.v" into library work
INFO: [VRFC 10-311] analyzing module simple_por
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/xres_buf.wire.v" into library work
INFO: [VRFC 10-311] analyzing module xres_buf
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/spare_logic_block.wire.v" into library work
INFO: [VRFC 10-311] analyzing module spare_logic_block
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/caravel_power_routing.wire.v" into library work
INFO: [VRFC 10-311] analyzing module caravel_power_routing
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/copyright_block.wire.v" into library work
INFO: [VRFC 10-311] analyzing module copyright_block
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/caravel_motto.wire.v" into library work
INFO: [VRFC 10-311] analyzing module caravel_motto
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/caravel_logo.wire.v" into library work
INFO: [VRFC 10-311] analyzing module caravel_logo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/open_source.wire.v" into library work
INFO: [VRFC 10-311] analyzing module open_source
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/user_id_textblock.wire.v" into library work
INFO: [VRFC 10-311] analyzing module user_id_textblock
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/empty_macro.v" into library work
INFO: [VRFC 10-311] analyzing module empty_macro
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/manual_power_connections.v" into library work
INFO: [VRFC 10-311] analyzing module manual_power_connections
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/caravel_core.wire.v" into library work
INFO: [VRFC 10-311] analyzing module caravel_core
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/caravel.wire.v" into library work
INFO: [VRFC 10-311] analyzing module caravel
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/tests/system/top_bench.sv" into library work
INFO: [VRFC 10-311] analyzing module top_bench
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /SSD1T/opt/Xilinx/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --timescale 1ns/10ps -debug typical -top top_bench -snapshot caravel_asic
Multi-threading is on. Using 30 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 12 for port 'axi_awaddr' [/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/fsic.vo:406]
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 12 for port 'axi_araddr' [/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/fsic.vo:411]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.sky130_fd_sc_hd__udp_pwrgood_pp_...
Compiling module work.sky130_fd_sc_hd__clkbuf
Compiling module work.sky130_fd_sc_hd__clkbuf_8
Compiling module work.buff_flash_clkrst_default
Compiling module work.sky130_fd_sc_hd__buf
Compiling module work.sky130_fd_sc_hd__buf_8
Compiling module work.sky130_ef_sc_hd__decap_12
Compiling module work.gpio_signal_buffering_default
Compiling module work.sky130_fd_io__top_power_hvc_wpad...
Compiling module work.sky130_ef_io__vddio_hvc_clamped_...
Compiling module work.sky130_ef_io__vdda_hvc_clamped_p...
Compiling module work.sky130_fd_io__top_power_lvc_wpad
Compiling module work.sky130_ef_io__vccd_lvc_clamped_p...
Compiling module work.sky130_fd_io__top_ground_hvc_wpa...
Compiling module work.sky130_ef_io__vssio_hvc_clamped_...
Compiling module work.sky130_ef_io__vssa_hvc_clamped_p...
Compiling module work.sky130_fd_io__top_ground_lvc_wpa...
Compiling module work.sky130_ef_io__vssd_lvc_clamped_p...
Compiling module work.sky130_ef_io__vccd_lvc_clamped3_...
Compiling module work.sky130_ef_io__vssd_lvc_clamped3_...
Compiling module work.sky130_fd_sc_hd__udp_pwrgood_pp_...
Compiling module work.sky130_fd_sc_hd__udp_pwrgood_pp_...
Compiling module work.sky130_fd_sc_hd__conb
Compiling module work.sky130_fd_sc_hd__conb_1
Compiling module work.sky130_fd_sc_hd__buf_16
Compiling module work.constant_block
Compiling module work.sky130_fd_io__top_gpiov2
Compiling module work.sky130_ef_io__gpiov2_pad_wrapped
Compiling module work.sky130_fd_io__top_xres4v2
Compiling module work.sky130_ef_io__corner_pad
Compiling module work.mprj_io_default
Compiling module work.chip_io_default
Compiling module work.sky130_fd_sc_hd__clkbuf_2
Compiling module work.sky130_fd_sc_hd__ebufn
Compiling module work.sky130_fd_sc_hd__ebufn_2
Compiling module work.sky130_fd_sc_hd__clkbuf_4
Compiling module work.sky130_fd_sc_hd__nor3b
Compiling module work.sky130_fd_sc_hd__nor3b_2
Compiling module work.sky130_fd_sc_hd__and3b
Compiling module work.sky130_fd_sc_hd__and3b_2
Compiling module work.sky130_fd_sc_hd__and3
Compiling module work.sky130_fd_sc_hd__and3_2
Compiling module work.sky130_fd_sc_hd__clkbuf_16
Compiling module work.sky130_fd_sc_hd__diode
Compiling module work.sky130_fd_sc_hd__diode_2
Compiling module work.sky130_fd_sc_hd__udp_dff_p_pp_pg...
Compiling module work.sky130_fd_sc_hd__dfxtp
Compiling module work.sky130_fd_sc_hd__dfxtp_1
Compiling module work.sky130_fd_sc_hd__nor4b
Compiling module work.sky130_fd_sc_hd__nor4b_2
Compiling module work.sky130_fd_sc_hd__and4bb
Compiling module work.sky130_fd_sc_hd__and4bb_2
Compiling module work.sky130_fd_sc_hd__and4b
Compiling module work.sky130_fd_sc_hd__and4b_2
Compiling module work.sky130_fd_sc_hd__and4
Compiling module work.sky130_fd_sc_hd__and4_2
Compiling module work.sky130_fd_sc_hd__udp_dlatch_p_pp...
Compiling module work.sky130_fd_sc_hd__dlxtp
Compiling module work.sky130_fd_sc_hd__dlxtp_1
Compiling module work.sky130_fd_sc_hd__and2
Compiling module work.sky130_fd_sc_hd__and2_1
Compiling module work.sky130_fd_sc_hd__inv
Compiling module work.sky130_fd_sc_hd__inv_1
Compiling module work.sky130_fd_sc_hd__dlclkp
Compiling module work.sky130_fd_sc_hd__dlclkp_1
Compiling module work.sky130_fd_sc_hd__udp_mux_4to2
Compiling module work.sky130_fd_sc_hd__mux4
Compiling module work.sky130_fd_sc_hd__mux4_1
Compiling module work.sky130_fd_sc_hd__tapvpwrvgnd
Compiling module work.sky130_fd_sc_hd__tapvpwrvgnd_1
Compiling module work.sky130_fd_sc_hd__decap
Compiling module work.sky130_fd_sc_hd__decap_12
Compiling module work.sky130_fd_sc_hd__decap_8
Compiling module work.sky130_fd_sc_hd__decap_3
Compiling module work.sky130_fd_sc_hd__fill
Compiling module work.sky130_fd_sc_hd__fill_2
Compiling module work.sky130_fd_sc_hd__decap_4
Compiling module work.sky130_fd_sc_hd__decap_6
Compiling module work.RAM128
Compiling module work.RAM256_default
Compiling module work.StreamFifoLowLatency
Compiling module work.VexRiscv
Compiling module work.mgmt_core
Compiling module work.mgmt_core_wrapper
Compiling module work.mprj_logic_high_default
Compiling module work.mprj2_logic_high
Compiling module work.sky130_fd_sc_hvl__udp_pwrgood_pp...
Compiling module work.sky130_fd_sc_hvl__udp_pwrgood_pp...
Compiling module work.sky130_fd_sc_hvl__conb
Compiling module work.sky130_fd_sc_hvl__conb_1
Compiling module work.sky130_fd_sc_hvl__udp_pwrgood_pp...
Compiling module work.sky130_fd_sc_hvl__lsbufhv2lv
Compiling module work.sky130_fd_sc_hvl__lsbufhv2lv_1
Compiling module work.mgmt_protect_hv
Compiling module work.sky130_fd_sc_hd__nand2
Compiling module work.sky130_fd_sc_hd__nand2_4
Compiling module work.mgmt_protect_default
Compiling module work.CFG_CTRL(pADDR_WIDTH=15)
Compiling module work.axilite_master
Compiling module work.axilite_slave
Compiling module work.axi_fifo(WIDTH=8'b0101010)
Compiling module work.axis_master
Compiling module work.axis_slave
Compiling module work.axi_fifo(WIDTH=8'b0110100)
Compiling module work.axi_fifo(WIDTH=8'b0100010)
Compiling module work.axi_ctrl_logic
Compiling module work.AXIL_AXIS
Compiling module work.AXIS_SW(pADDR_WIDTH=12)
Compiling module work.fsic_coreclk_phase_cnt
Compiling module work.fsic_io_serdes_rx
Compiling module work.IO_SERDES(pADDR_WIDTH=12)
Compiling module work.LOGIC_ANLZ
Compiling module work.AXIL_SLAV
Compiling module work.USER_PRJ
Compiling module work.AXIS_SLAV
Compiling module work.AXIS_MSTR
Compiling module work.IRQ_MUX
Compiling module work.LA_MUX
Compiling module work.USER_SUBSYS(pADDR_WIDTH=15)
Compiling module work.FSIC_CLKRST
Compiling module work.MPRJ_IO
Compiling module work.FSIC
Compiling module work.user_project_wrapper
Compiling module work.even
Compiling module work.odd
Compiling module work.clock_div
Compiling module work.caravel_clocking
Compiling module work.ring_osc2x13
Compiling module work.digital_pll_controller
Compiling module work.digital_pll
Compiling module work.housekeeping_spi
Compiling module work.housekeeping
Compiling module work.gpio_defaults_block_default
Compiling module work.gpio_logic_high
Compiling module work.sky130_fd_sc_hd__inv_2
Compiling module work.sky130_fd_sc_hd__nor2
Compiling module work.sky130_fd_sc_hd__nor2_2
Compiling module work.sky130_fd_sc_hd__nand2_2
Compiling module work.sky130_fd_sc_hd__macro_sparecell
Compiling module work.gpio_control_block_default
Compiling module work.user_id_programming_default
Compiling module work.sky130_fd_sc_hvl__schmittbuf
Compiling module work.sky130_fd_sc_hvl__schmittbuf_1
Compiling module work.simple_por
Compiling module work.xres_buf
Compiling module work.sky130_fd_sc_hd__inv_8
Compiling module work.sky130_fd_sc_hd__udp_mux_2to1
Compiling module work.sky130_fd_sc_hd__mux2
Compiling module work.sky130_fd_sc_hd__mux2_2
Compiling module work.sky130_fd_sc_hd__udp_dff_nsr_pp_...
Compiling module work.sky130_fd_sc_hd__dfbbp
Compiling module work.sky130_fd_sc_hd__dfbbp_1
Compiling module work.spare_logic_block_default
Compiling module work.caravel_default
Compiling module work.spiflash(FILENAME="riscv.hex")
Compiling module work.fsic_clock_div
Compiling module work.IO_SERDES_default
Compiling module work.fpga
Compiling module work.tbuart
Compiling module work.top_bench
Built simulation snapshot caravel_asic
~/workspace/fsic/fsic_asic/verif/vsim/rsim ~/workspace/fsic/fsic_asic/verif/vsim/rsim
In file included from ../system/isr.c:8:
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:273: warning: "reg_debug_2" redefined
273 | #define reg_debug_2 (*(volatile unsigned int*)(USER_SPACE_ADDR + USER_SPACE_SIZE))
|
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:147: note: this is the location of the previous definition
147 | #define reg_debug_2 (*(volatile uint32_t*)0x300FFFFC)
|
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:274: warning: "reg_debug_1" redefined
274 | #define reg_debug_1 (*(volatile unsigned int*)(USER_SPACE_ADDR + USER_SPACE_SIZE - 4))
|
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:146: note: this is the location of the previous definition
146 | #define reg_debug_1 (*(volatile uint32_t*)0x300FFFF8)
|
In file included from system.c:20:
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:273: warning: "reg_debug_2" redefined
273 | #define reg_debug_2 (*(volatile unsigned int*)(USER_SPACE_ADDR + USER_SPACE_SIZE))
|
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:147: note: this is the location of the previous definition
147 | #define reg_debug_2 (*(volatile uint32_t*)0x300FFFFC)
|
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:274: warning: "reg_debug_1" redefined
274 | #define reg_debug_1 (*(volatile unsigned int*)(USER_SPACE_ADDR + USER_SPACE_SIZE - 4))
|
../../../../../../fork/caravel_mgmt_soc_litex/verilog/dv/firmware/defs.h:146: note: this is the location of the previous definition
146 | #define reg_debug_1 (*(volatile uint32_t*)0x300FFFF8)
|
~/workspace/fsic/fsic_asic/verif/vsim/rsim
****** xsim v2022.2 (64-bit)
**** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
**** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source xsim.dir/caravel_asic/xsim_script.tcl
# xsim {caravel_asic} -autoloadwcfg -tclbatch {log_wave.tcl}
Time resolution is 1 ps
open_wave_config /home/tonyho/workspace/fsic/fsic_asic/verif/vsim/rsim/caravel_asic.wcfg
source log_wave.tcl
## log_wave -quiet -verbose -recursive *
## run all
Reading riscv.hex
riscv.hex loaded into memory
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13
USER_PROJ_IRQ0 Test
test114: TX/RX test - loop 00
0=> 1st la_output=00000000000000000000000000000000
0=> 2nd la_output=00000000000000000000000000000001
40=> fpga POR Assert
40=> fpga reset Assert
80=> fpga POR De-Assert
120=> fpga reset De-Assert
550=> 1st la_output=00000000000000000000000000000000
550=> 2nd la_output=00000000000000000000000000000000
563=> fpga_as_to_is_init done
800.000 ns MSG top_bench, Chip Reset# is released
963=> wait uut.mprj.u_fsic.U_IO_SERDES0.rxen
100450.000 ns MSG top_bench, +1000 cycles
200450.000 ns MSG top_bench, +1000 cycles
300450.000 ns MSG top_bench, +1000 cycles
400450.000 ns MSG top_bench, +1000 cycles
500450.000 ns MSG top_bench, +1000 cycles
600450.000 ns MSG top_bench, +1000 cycles
700450.000 ns MSG top_bench, +1000 cycles
800450.000 ns MSG top_bench, +1000 cycles
900450.000 ns MSG top_bench, +1000 cycles
1000450.000 ns MSG top_bench, +1000 cycles
1100450.000 ns MSG top_bench, +1000 cycles
1200450.000 ns MSG top_bench, +1000 cycles
1300450.000 ns MSG top_bench, +1000 cycles
1400450.000 ns MSG top_bench, +1000 cycles
1500450.000 ns MSG top_bench, +1000 cycles
1600450.000 ns MSG top_bench, +1000 cycles
1700450.000 ns MSG top_bench, +1000 cycles
1800450.000 ns MSG top_bench, +1000 cycles
1900450.000 ns MSG top_bench, +1000 cycles
2000450.000 ns MSG top_bench, +1000 cycles
2100450.000 ns MSG top_bench, +1000 cycles
2200450.000 ns MSG top_bench, +1000 cycles
2300450.000 ns MSG top_bench, +1000 cycles
2400450.000 ns MSG top_bench, +1000 cycles
2500450.000 ns MSG top_bench, +1000 cycles
2600450.000 ns MSG top_bench, +1000 cycles
2700450.000 ns MSG top_bench, +1000 cycles
2800450.000 ns MSG top_bench, +1000 cycles
2900450.000 ns MSG top_bench, +1000 cycles
2942275=> detect uut.mprj.u_fsic.U_IO_SERDES0.rxen=1
2942363=> fpga_cfg_write : fpga_axi_awaddr=0000, fpga_axi_awvalid=1, fpga_axi_awready=1, fpga_axi_wdata=00000001, axi_wstrb=1, fpga_axi_wvalid=1, fpga_axi_wready=1
2942363=> fpga rxen_ctl=1
2942863=> fpga_cfg_write : fpga_axi_awaddr=0000, fpga_axi_awvalid=1, fpga_axi_awready=1, fpga_axi_wdata=00000003, axi_wstrb=1, fpga_axi_wvalid=1, fpga_axi_wready=1
2942863=> fpga txen_ctl=1
2943303=> wait uut.mprj.u_fsic.U_AXIL_AXIS0.axi_ctrl_logic.aa_regs[0][0] (interrupt enable bit)
3000450.000 ns MSG top_bench, +1000 cycles
3100450.000 ns MSG top_bench, +1000 cycles
3200450.000 ns MSG top_bench, +1000 cycles
3300450.000 ns MSG top_bench, +1000 cycles
3400450.000 ns MSG top_bench, +1000 cycles
3500450.000 ns MSG top_bench, +1000 cycles
3600450.000 ns MSG top_bench, +1000 cycles
3700450.000 ns MSG top_bench, +1000 cycles
3800450.000 ns MSG top_bench, +1000 cycles
3900450.000 ns MSG top_bench, +1000 cycles
4000450.000 ns MSG top_bench, +1000 cycles
4100450.000 ns MSG top_bench, +1000 cycles
4200450.000 ns MSG top_bench, +1000 cycles
4300450.000 ns MSG top_bench, +1000 cycles
4400450.000 ns MSG top_bench, +1000 cycles
4500450.000 ns MSG top_bench, +1000 cycles
4599550=> detect uut.mprj.u_fsic.U_AXIL_AXIS0.axi_ctrl_logic.aa_regs[0][0]=1
4599563=> test114_fpga_to_soc_CFG_write start
4599763=> test114_fpga_to_soc_CFG_write fpga_axilite_write_addr = 0002000, be=f, data = 00000001
4600450.000 ns MSG top_bench, +1000 cycles
4700450.000 ns MSG top_bench, +1000 cycles
4800450.000 ns MSG top_bench, +1000 cycles
4900450.000 ns MSG top_bench, +1000 cycles
5000450.000 ns MSG top_bench, +1000 cycles
5100450.000 ns MSG top_bench, +1000 cycles
5200450.000 ns MSG top_bench, +1000 cycles
5300450.000 ns MSG top_bench, +1000 cycles
5400450.000 ns MSG top_bench, +1000 cycles
5500450.000 ns MSG top_bench, +1000 cycles
5600450.000 ns MSG top_bench, +1000 cycles
5700450.000 ns MSG top_bench, +1000 cycles
5800450.000 ns MSG top_bench, +1000 cycles
5801063=> get soc_to_fpga_mailbox_write_addr_captured be : soc_to_fpga_mailbox_write_addr_captured =xxxxxxxx, fpga_is_as_tdata=f0002004
5801063=> get soc_to_fpga_mailbox_write_addr_captured af : soc_to_fpga_mailbox_write_addr_captured =f0002004, fpga_is_as_tdata=f0002004
5801163=> get soc_to_fpga_mailbox_write_data_captured be : soc_to_fpga_mailbox_write_data_captured =xxxxxxxx, fpga_is_as_tdata=00000001
5801163=> get soc_to_fpga_mailbox_write_data_captured af : soc_to_fpga_mailbox_write_data_captured =00000001, fpga_is_as_tdata=00000001
5801163=> soc_to_fpga_mailbox_write_data_captured : send soc_to_fpga_mailbox_write_event
5801163=> wait_and_check_soc_to_fpga_mailbox_write_event : got soc_to_fpga_mailbox_write_event
5801163=> wait_and_check_soc_to_fpga_mailbox_write_event [PASS] soc_to_fpga_mailbox_write_addr_expect_value=0002004, soc_to_fpga_mailbox_write_addr_captured[27:0]=0002004
5801163=> wait_and_check_soc_to_fpga_mailbox_write_event [PASS] soc_to_fpga_mailbox_write_addr_BE_expect_value=f, soc_to_fpga_mailbox_write_addr_captured[31:28]=f
5801163=> wait_and_check_soc_to_fpga_mailbox_write_event [PASS] soc_to_fpga_mailbox_write_data_expect_value=00000001, soc_to_fpga_mailbox_write_data_captured=00000001
-----------------
5801263=> test114_fpga_to_soc_CFG_write wait 320us
5900450.000 ns MSG top_bench, +1000 cycles
6000450.000 ns MSG top_bench, +1000 cycles
6100450.000 ns MSG top_bench, +1000 cycles
6200450.000 ns MSG top_bench, +1000 cycles
6300450.000 ns MSG top_bench, +1000 cycles
6400450.000 ns MSG top_bench, +1000 cycles
6500450.000 ns MSG top_bench, +1000 cycles
6600450.000 ns MSG top_bench, +1000 cycles
6601463=> test114_fpga_to_soc_CFG_write fpga_axilite_write_addr = 0002000, be=f, data = 5a5a5a5a
6700450.000 ns MSG top_bench, +1000 cycles
6800450.000 ns MSG top_bench, +1000 cycles
6900450.000 ns MSG top_bench, +1000 cycles
7000450.000 ns MSG top_bench, +1000 cycles
7100450.000 ns MSG top_bench, +1000 cycles
7200450.000 ns MSG top_bench, +1000 cycles
7300450.000 ns MSG top_bench, +1000 cycles
7400450.000 ns MSG top_bench, +1000 cycles
7500450.000 ns MSG top_bench, +1000 cycles
7600450.000 ns MSG top_bench, +1000 cycles
7700450.000 ns MSG top_bench, +1000 cycles
7798963=> get soc_to_fpga_mailbox_write_addr_captured be : soc_to_fpga_mailbox_write_addr_captured =f0002004, fpga_is_as_tdata=f0002004
7798963=> get soc_to_fpga_mailbox_write_addr_captured af : soc_to_fpga_mailbox_write_addr_captured =f0002004, fpga_is_as_tdata=f0002004
7799063=> get soc_to_fpga_mailbox_write_data_captured be : soc_to_fpga_mailbox_write_data_captured =00000001, fpga_is_as_tdata=5a5a5a5a
7799063=> get soc_to_fpga_mailbox_write_data_captured af : soc_to_fpga_mailbox_write_data_captured =5a5a5a5a, fpga_is_as_tdata=5a5a5a5a
7799063=> soc_to_fpga_mailbox_write_data_captured : send soc_to_fpga_mailbox_write_event
7799063=> wait_and_check_soc_to_fpga_mailbox_write_event : got soc_to_fpga_mailbox_write_event
7799063=> wait_and_check_soc_to_fpga_mailbox_write_event [PASS] soc_to_fpga_mailbox_write_addr_expect_value=0002004, soc_to_fpga_mailbox_write_addr_captured[27:0]=0002004
7799063=> wait_and_check_soc_to_fpga_mailbox_write_event [PASS] soc_to_fpga_mailbox_write_addr_BE_expect_value=f, soc_to_fpga_mailbox_write_addr_captured[31:28]=f
7799063=> wait_and_check_soc_to_fpga_mailbox_write_event [PASS] soc_to_fpga_mailbox_write_data_expect_value=5a5a5a5a, soc_to_fpga_mailbox_write_data_captured=5a5a5a5a
-----------------
7799163=> test114_fpga_to_soc_CFG_write done
7800450.000 ns MSG top_bench, +1000 cycles
7900450.000 ns MSG top_bench, +1000 cycles
8000450.000 ns MSG top_bench, +1000 cycles
8100450.000 ns MSG top_bench, +1000 cycles
8200450.000 ns MSG top_bench, +1000 cycles
8300450.000 ns MSG top_bench, +1000 cycles
8400450.000 ns MSG top_bench, +1000 cycles
8500450.000 ns MSG top_bench, +1000 cycles
8600450.000 ns MSG top_bench, +1000 cycles
8700450.000 ns MSG top_bench, +1000 cycles
8800450.000 ns MSG top_bench, +1000 cycles
8900450.000 ns MSG top_bench, +1000 cycles
9000450.000 ns MSG top_bench, +1000 cycles
9100450.000 ns MSG top_bench, +1000 cycles
9200450.000 ns MSG top_bench, +1000 cycles
9300450.000 ns MSG top_bench, +1000 cycles
9400450.000 ns MSG top_bench, +1000 cycles
9500450.000 ns MSG top_bench, +1000 cycles
9600450.000 ns MSG top_bench, +1000 cycles
9700450.000 ns MSG top_bench, +1000 cycles
9800450.000 ns MSG top_bench, +1000 cycles
9900450.000 ns MSG top_bench, +1000 cycles
10000450.000 ns MSG top_bench, +1000 cycles
=============================================================================================
=============================================================================================
=============================================================================================
10000450=> Final result [PASS], error_cnt = 00000000
=============================================================================================
=============================================================================================
=============================================================================================
$finish called at time : 10000450 ns : File "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/tests/system/top_bench.sv" Line 269
run: Time (s): cpu = 00:05:48 ; elapsed = 00:06:03 . Memory (MB): peak = 2037.625 ; gain = 0.000 ; free physical = 16592 ; free virtual = 54965
## quit
INFO: xsimkernel Simulation Memory Usage: 338608 KB (Peak: 338608 KB), Simulation CPU Usage: 199850 ms
INFO: [Common 17-206] Exiting xsim at Thu Aug 24 21:25:04 2023...
(base) tonyho@ubuntu5:~/workspace/fsic/fsic_asic/verif/vsim/rsim$
```
# user_irq_ena_storage[2:0] address decode
slave_sel[6] -> mgmtsoc_wishbone_adr -> mgmtsoc_adr -> csr_interconnect_adr -> interface19_bank_bus_adr ->csrbank19_sel -> user_irq_ena_storage[2:0]
[addr calculate excel link](https://docs.google.com/spreadsheets/d/1B0Fvv7ZtvyGC6uvhX_zbKZfEU7aTv3TmEReqFLn2mzU/edit?usp=sharing)
## mgmtsoc_wishbone_cyc
```
assign mgmtsoc_wishbone_cyc = (shared_cyc & slave_sel[6]);
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L4907C1-L4907C59)
## mgmtsoc_wishbone_adr
```
assign mgmtsoc_wishbone_adr = shared_adr;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L4894C1-L4894C42)
```
always_comb begin
mgmtsoc_adr = 14'd0;
case (state)
1'd1: begin
end
default: begin
if ((mgmtsoc_wishbone_cyc & mgmtsoc_wishbone_stb)) begin
mgmtsoc_adr = mgmtsoc_wishbone_adr;
end
end
endcase
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L4800C1-L4811C4)
```
assign csr_interconnect_adr = mgmtsoc_adr;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L6385C1-L6385C43)
## csrbank19_sel
```
wire [13:0] interface19_bank_bus_adr;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L1469C1-L1469C38)
```
assign interface19_bank_bus_adr = csr_interconnect_adr;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L6408C1-L6408C56)
```
//slave_sel[6] for wb_addr[29:14] = 0xF000
//5'd19 = 5'h13
assign csrbank19_sel = (interface19_bank_bus_adr[13:9] == 5'd19);
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L6370C1-L6370C66)
```
if (csrbank19_sel) begin
case (interface19_bank_bus_adr[8:0])
1'd0: begin
interface19_bank_bus_dat_r <= csrbank19_out0_w;
end
endcase
end
if (csrbank19_out0_re) begin
user_irq_ena_storage[2:0] <= csrbank19_out0_r;
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L7851C1-L7860C5)
## user_irq_ena_storage connect to user_irq_enable
```
assign user_irq_ena = user_irq_ena_storage;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L4636C1-L4636C44)
# user_irq from user project -> mgmt_protect -> mgmt_core
## caravel.v : user_irq, user_irq_ena
```
module caravel (
);
...
wire [2:0] user_irq_ena;
wire [2:0] user_irq; // From MRPJ to CPU
...
mgmt_core_wrapper soc (
...
.irq({irq_spi, user_irq}), //input
.user_irq_ena(user_irq_ena), //output
...
);
...
mgmt_protect mgmt_buffers (
...
.user_irq_core(user_irq_core), //input
.user_irq_ena(user_irq_ena), //input
...
.user_irq(user_irq), //output
...
);
...
user_project_wrapper mprj (
...
.user_irq(user_irq_core) //output
...
);
...
endmodule
```
[code link - soc instance](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/caravel.v#L554)
[code link - mgmt_buffers instance](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/caravel.v#L625)
[code link - mprj instance](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/caravel.v#L697)
## mgmt_core.patrick.v : gpioin0_gpioin0_trigger is coming from usr_irq[0]
### Normal waveform
### usr_irq[0] to gpioin0_in_status
```
multiregimpl131_regs0 <= user_irq[0];
multiregimpl131_regs1 <= multiregimpl131_regs0;
```
[code link]()
- why no reset in multiregimpl131_regs0?
```
...
reg multiregimpl131_regs0 = 1'd0;
reg multiregimpl131_regs1 = 1'd0;
...
always @(posedge sys_clk) begin
...
multiregimpl131_regs0 <= user_irq[0];
multiregimpl131_regs1 <= multiregimpl131_regs0;
...
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L1759C1-L1761C1)
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L8375C1-L8376C49)
```
assign gpioin0_in_status = multiregimpl131_regs1;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L6729)
### gpioin0_in_status to gpioin0_gpioin0_trigger
- gpioin0_gpioin0_trigger come from (gpioin0_in_status ^ gpioin0_gpioin0_edge_storage)
```
always_comb begin
gpioin0_gpioin0_trigger = 1'd0;
if (gpioin0_gpioin0_mode_storage) begin
gpioin0_gpioin0_trigger = (gpioin0_in_status ^ gpioin0_gpioin0_in_pads_n_d);
end else begin
gpioin0_gpioin0_trigger = (gpioin0_in_status ^ gpioin0_gpioin0_edge_storage);
end
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L4642C18-L4642C18)
```
assign gpioin0_in_status = multiregimpl131_regs1;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L6729)
### gpioin0_gpioin0_trigger to gpioin0_gpioin0_pending
```
reg gpioin0_gpioin0_pending = 1'd0;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L721C1-L721C36)
```
always @(posedge sys_clk) begin
...
if (gpioin0_gpioin0_clear) begin
gpioin0_gpioin0_pending <= 1'd0;
end
gpioin0_gpioin0_trigger_d <= gpioin0_gpioin0_trigger;
if ((gpioin0_gpioin0_trigger & (~gpioin0_gpioin0_trigger_d))) begin
gpioin0_gpioin0_pending <= 1'd1;
end
...
if (sys_rst) begin
gpioin0_gpioin0_pending <= 1'd0;
end
...
end
```
[code link - for set and clear](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L7103C1-L7109C5)
[code link - for reset](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L8027)
### clear gpioin0_gpioin0_pending
## mgmt_core.patrick.v : user_irq[0] coming from other module
```
module mgmt_core(
...
input wire [5:0] user_irq,
...
);
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L64)
## mgmt_core_wrapper.v : irq
```
module mgmt_core_wrapper (
...
input [5:0] irq, // IRQ from SPI and user project
...
);
...
mgmt_core core (
...
.user_irq(irq), // IRQ from SPI and user project
...
);
...
endmodule
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core_wrapper.v#L197C1-L197C61)
## mgmt_protect.v : user_irq_core, user_irq, user_irq_ena
```
module mgmt_protect (
...
input [2:0] user_irq_core,
...
input [2:0] user_irq_ena,
...
output [2:0] user_irq,
...
);
...
wire [2:0] user_irq_bar;
...
assign user_irq_enable = user_irq_ena & mprj_logic1[460:458];
sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
...
.Y(user_irq_bar),
.A(user_irq_core), // may be floating
.B(user_irq_enable)
);
assign user_irq = ~user_irq_bar;
...
endmodule
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_protect.v#L179C1-L191C4)
## mgmt_core_wrapper.v : user_irq_ena
```
module mgmt_core_wrapper (
...
input [5:0] irq, // IRQ from SPI and user project
output [2:0] user_irq_ena, // Enables for user project IRQ
...
);
...
mgmt_core core (
...
.user_irq(irq), // IRQ from SPI and user project
.user_irq_ena(user_irq_ena),
...
);
...
endmodule
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core_wrapper.v#L197C1-L197C61)
## mgmt_core.patrick.v : user_irq_ena
```
module mgmt_core(
...
output wire [2:0] user_irq_ena,
input wire [5:0] user_irq,
...
);
...
assign user_irq_ena = user_irq_ena_storage;
...
assign csrbank19_out0_w = user_irq_ena_storage[2:0];
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L4636)
```
always @(posedge sys_clk) begin
...
if (csrbank19_out0_re) begin
user_irq_ena_storage[2:0] <= csrbank19_out0_r;
end
...
if (sys_rst) begin
user_irq_ena_storage <= 3'd0;
end
...
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/dsn/rtl/mgmt_core.patrick.v#L7858C1-L7860C5)
# mgmt_core.patrick.v : gpioin0_gpioin0_pending->gpioin0_pending_status->gpioin0_gpioin0_irq
## gpioin0_gpioin0_pending to gpioin0_pending_status
```
assign gpioin0_i01 = gpioin0_gpioin0_pending;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L4646C1-L4646C46)
```
assign gpioin0_pending_status = gpioin0_i01;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L5910C1-L5910C45)
## gpioin0_pending_status to gpioin0_gpioin0_irq
```
assign gpioin0_gpioin0_irq = (gpioin0_pending_status & gpioin0_enable_storage);
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L4653C1-L4653C80)
## gpioin0_enable_storage
```
if (csrbank13_ev_enable0_re) begin
gpioin0_enable_storage <= csrbank13_ev_enable0_r;
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L7641C1-L7643C5)
### csrbank13_ev_enable0_re
slave_sel[6] -> csrbank13 -> offset = 5
```
always_comb begin
csrbank13_ev_enable0_re = 1'd0;
if ((csrbank13_sel & (interface13_bank_bus_adr[8:0] == 3'd5))) begin
csrbank13_ev_enable0_re = interface13_bank_bus_we;
end
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L5891C1-L5896C4)
# mgmt_core.patrick.v : gpioin0_gpioin0_trigger->USER_IRQ_0_EV_STATUS
## gpioin0_gpioin0_trigger to csrbank13_ev_status_w
```
assign gpioin0_gpioin0_status = gpioin0_gpioin0_trigger;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L4654C33-L4654C56)
```
assign gpioin0_i00 = gpioin0_gpioin0_status;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L4645C1-L4645C45)
```
assign gpioin0_status_status = gpioin0_i00;
assign csrbank13_ev_status_w = gpioin0_status_status;
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L5907C1-L5907C44)
## csrbank13_ev_status_w for USER_IRQ_0_EV_STATUS read
```
if (csrbank13_sel) begin
case (interface13_bank_bus_adr[8:0])
1'd0: begin
interface13_bank_bus_dat_r <= csrbank13_in_w;
end
1'd1: begin
interface13_bank_bus_dat_r <= csrbank13_mode0_w;
end
2'd2: begin
interface13_bank_bus_dat_r <= csrbank13_edge0_w;
end
2'd3: begin
interface13_bank_bus_dat_r <= csrbank13_ev_status_w;
end
3'd4: begin
interface13_bank_bus_dat_r <= csrbank13_ev_pending_w;
end
3'd5: begin
interface13_bank_bus_dat_r <= csrbank13_ev_enable0_w;
end
endcase
end
```
[code link](https://github.com/bol-edu/fsic_asic/blob/63076dceb390d3942327ed20a61b9e32f267520c/src/mgmt_core.patrick.v#L7605C1-L7626C5)
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