Caravel-soc_fpga always block value assign issue : simulation fail in using systemverilog but pass in verilog issue

# fail waveform when use systemverilog
[code commit](https://github.com/TonyHo722/caravel-soc_fpga/commit/a53f49b6406786f109cb86b2b8c800a2c4954b2f)

- execution as below

(base) tonyho@ubuntu5:~/workspace/fsic/caravel-soc_fpga_josh_2022.2/testbench/counter_la$ ./run_sv


- the waveform in CsrPlugin_mstatus_MIE is different

# pass wavefrom in verilog
- execution as below

(base) tonyho@ubuntu5:~/workspace/fsic/caravel-soc_fpga_josh_2022.2/testbench/counter_la$ ./run_xsim 


# the different in run_xsim and run_sv

(base) tonyho@ubuntu5:~/workspace/fsic/caravel-soc_fpga_josh_2022.2/testbench/counter_la$ diff run_xsim run_sv
17c17,19
< xvlog -d FUNCTIONAL -d SIM -d DUNIT_DELAY=#1 -d USE_POWER_PINS -f ./include.rtl.list.xsim counter_la_tb.v \
---
> xvlog -d FUNCTIONAL -d SIM -d DUNIT_DELAY=#1 -d USE_POWER_PINS -f ./include.rtl.list.xsim counter_la_tb.sv \
>       -sv \
>       -d CPU_TRACE \
20a23
> 

# waveform different in la_output[127:0]

## initial value issue in verilog and systemverlog
[code commit](https://github.com/TonyHo722/caravel-soc_fpga/commit/8240837a4e5d2482fbeab7a2a6d1892ba35837f6)

commit 8240837a4e5d2482fbeab7a2a6d1892ba35837f6 (HEAD -> debug_sv, origin/debug_sv)
Author: tonyho <[e-mail]>
Date:   Mon Aug 21 18:57:19 2023 +0800

commit 16ed151e72455ad87503e8de5c33b9574ed6dc29
Author: tonyho <[e-mail]>
Date:   Mon Aug 21 18:52:46 2023 +0800

    add debug message for blocking assigment

diff --git a/rtl/soc-efabless/mgmt_core.v b/rtl/soc-efabless/mgmt_core.v
index d3e43d7..4f413cb 100644
--- a/rtl/soc-efabless/mgmt_core.v
+++ b/rtl/soc-efabless/mgmt_core.v
@@ -4499,6 +4499,7 @@ always @(*) begin
 end
 always @(*) begin
        la_output = 128'd0;
+       $display($time, "=> 1st a_output=%x", la_output);^M
        la_output[0] = la_out_storage[0];
        la_output[1] = la_out_storage[1];
        la_output[2] = la_out_storage[2];
@@ -4627,6 +4628,7 @@ always @(*) begin
        la_output[125] = la_out_storage[125];
        la_output[126] = la_out_storage[126];
        la_output[127] = la_out_storage[127];
+       $display($time, "=> 2nd la_output=%x", la_output);^M
 end
 assign spi_enabled = spi_enabled_storage;
 assign user_irq_ena = user_irq_ena_storage;

### verilog xsim log

# xsim {counter_la_tb_elab} -autoloadwcfg -runall
Time resolution is 1 ps
run -all
Reading counter_la.hex
counter_la.hex loaded into memory
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13
                   0=> 1st la_output=00000000000000000000000000000000
                   0=> 2nd la_output=00000000000000000000000000000000
LA Test 1 started
LA Test 2 passed
USER_PROJ_IRQ0 Test passed

## SystemVerilog xsim log
- no output in la_output

# xsim {counter_la_tb_elab} -autoloadwcfg -runall
Time resolution is 1 ps
run -all
Reading counter_la.hex
counter_la.hex loaded into memory
Memory 5 bytes = 0x6f 0x00 0x00 0x0b 0x13
        0.000ns MSG counter_la_tb, cpu_exec.log generated
LA Test 1 started
LA Test 2 passed

Monitor: Timeout, Test LA (RTL) Failed

# check reset in mgmt_core.v

reg int_rst = 1'd1;

[code link](https://github.com/TonyHo722/caravel-soc_fpga/blob/b36ba76c72574fd3b8046d3841cdb93d36e59e0f/rtl/soc-efabless/mgmt_core.v#L89)

assign sys_rst = int_rst;

[code link](https://github.com/TonyHo722/caravel-soc_fpga/blob/b36ba76c72574fd3b8046d3841cdb93d36e59e0f/rtl/soc-efabless/mgmt_core.v#L1840)

always @(posedge por_clk) begin
	int_rst <= core_rst;
end

[code link](https://github.com/TonyHo722/caravel-soc_fpga/blob/b36ba76c72574fd3b8046d3841cdb93d36e59e0f/rtl/soc-efabless/mgmt_core.v#L6743C1-L6745C4)

reg [127:0] la_out_storage = 128'd0;

[code link](https://github.com/TonyHo722/caravel-soc_fpga/blob/b36ba76c72574fd3b8046d3841cdb93d36e59e0f/rtl/soc-efabless/mgmt_core.v#L705)

always @(*) begin
	la_output = 128'd0;
	la_output[0] = la_out_storage[0];
	la_output[1] = la_out_storage[1];
	la_output[2] = la_out_storage[2];

[code link](https://github.com/TonyHo722/caravel-soc_fpga/blob/b36ba76c72574fd3b8046d3841cdb93d36e59e0f/rtl/soc-efabless/mgmt_core.v#L4500)

always @(posedge sys_clk) begin
    ...
	if (sys_rst) begin
        ...
        la_out_storage <= 128'd0;
        ...
    end        
    ...
end        

[code link](https://github.com/TonyHo722/caravel-soc_fpga/blob/b36ba76c72574fd3b8046d3841cdb93d36e59e0f/rtl/soc-efabless/mgmt_core.v#L8022)

# code to repro this issue


- xvlog using systemverilog by `-sv` then no execution always block when T = 0 as belowvi .

    always @(*) begin
        $display("=> checkpoint 1");
        la_output = 128'd0;
        $display("=> checkpoint 2");
        la_output = la_out_storage;
        $display("=> checkpoint 3");
    end   

[code Link](https://github.com/TonyHo722/xvlog_systemverilog/blob/main/xvlog_tb.v#L42)

# patch soultion

## method 1 - change .v code to using alwyas_comb

    alwyas_comb begin
        $display("=> checkpoint 1");
        la_output = 128'd0;
        $display("=> checkpoint 2");
        la_output = la_out_storage;
        $display("=> checkpoint 3");
    end