---
# System prepended metadata

title: 摩爾旅程 Moore's Journey
tags: [讀書心得, Semiconductor]

---

# 摩爾旅程 Moore's Journey
###### tags: `讀書心得`, `Semiconductor`
![image](https://hackmd.io/_uploads/r1KalT7GZe.png)
:::success
* 可搭配NTUMSE陳敏璋教授 **"半導體元件物理"** 課程講義
* 可搭配NTUCHE陳嘉晉教授 **"化工程序設計實作"** 課程講義
* 可搭配UTokyo松久直司教授 **"半導體元件基礎"** 課程講義
* 可搭配NYCU吳添立教授 **"半導體物理與元件"** [課程](https://youtube.com/playlist?list=PLOj85jQ5D7J90qh_uX-I_uLJu8WdY5XS-&si=Q3nn5dO7CtHCplh1)(還在上)
* 施敏教授也有半導體元件物理課程但還沒開始上

這本書是因緣際會，在YT上點進NTUMSE白奇峰教授的[Solid State Physics 2024](https://youtube.com/playlist?list=PLCr_gutW3TyPLILulidkeZLgdhckzSFQI&si=VPI6xMXeStqkxQt8)的課程，想說複習一下時被推薦的，在誠品讀完作者序跟翻了一下chapter 1, chapter 2後，非常喜歡，就買下來了（笑

林茂雄博士文筆非常好，希望讀完這本書後可以跟著他的文字，聽到電子的足音、摸到電子的身體，甚至細數電子的數目！

以下節錄自作者序中我最喜歡的一段話：
**「我們活在一個巨觀的世界中，所感知到的都是統計的結果，就只能感嘆青春不再。時間一去不復返是模糊 （blurred） 和無知 （ignorance）造成的，就像 Carlo Rovelli 所說的「時間卽無知」（time is ignorance）。如果我們能像神一樣的無所不知，觀察入微，也就沒有過去和未來的區分了！**

**1915 年愛因斯坦的廣義相對論提出史詩般的「空間卽重力」（space isgravity）觀點。1927 年海森堡（Heisenberg）發表極具爭議性的「測不準原則」（uncertainty principle） 論述。「時間即無知」（time is ignorance）、「空間卽重力」（space is gravity） 和「測不準原則」（uncertainty principle） 的3個物理原則簡直是神奇的近乎荒謬，但卻是宇宙萬事萬物的最基本原則，也是我寫這本書的三個根本物理哲學。**

**當然，事實也證明，不懂電晶體的量子力學的布洛赫波 （Bloch wave）及統計熱力學的費米-迪拉克分佈統計原理 （Fermi-Dirac distributionstatistics），照樣可以成爲半導體產業界呼風喚雨、腰纏萬貫的企業家或商人。2017年2月，美國 NBA 籃球名將 Kyrie Irving 曾在 Podcast 上質疑地球是平的；不知道「地球是圓的」，且繞著太陽旋轉，並無損 Kyrie Irving 打籃球的天分和成就。但是最大的差別在於是否有好奇心。好奇心是我過去生活和做事的原動力，一層一層的問下去，一層一層的想下去，打破砂鍋問到底，非想個淸楚不停，這也構成我寫作這本書的基礎。」**
:::

[TOC]
# Chapter 1
半導體發展的重要里程碑
1. 電晶體的發明 (1947)
2. 積體電路的發明 (1958)
3. 金屬氧化物半導體場效電晶體 (MOSFET) 的發明 (1959)
4. Intel 的成立（1968），主導了1968至2016年的摩爾定律及 Wintel個人電腦架構
5. 蘋果 (Apple) 個人電腦的誕生 (1976)
6. 微軟 (Microsoft) 的視窗 (1985)，Wintel 個人電腦增加半導體的需求
7. 台積電的純代工商業模式 (1987)
8. 網際網路的發明 (1990)，把個人電腦連線上網
9. 鰭式場效應電晶體 (FINFET) 的發明 (1998)，把平面電晶體立體化，延續摩爾定律至20 nm以下技術節點
10. 高通 (Qualcomm) 的分碼多重進接 (CDMA) 通訊晶片 （2000），加大連線上網頻寬
11. 蘋果 iPhone 1 智慧型手機的誕生 (2007)
12. 蘋果的 A14 晶片和輝達 (NVIDIA) 的 A100 晶片 (2020)，每個晶片都含有100億個以上的電晶體。
## 關於iPhone的誕生
* 書中提到Jobs將iPhone的四角設計成圓滑的弧形，我才意識到：對誒我小時候在日本拿到的折疊式傻瓜型手機四角都是有棱有角的，這樣一說iPhone的長相真的可以說是優雅又不失美感～
* (也很慶幸我爸媽沒有讓我太早接觸智慧型手機，我國三後才有自己的智慧型手機，因為這樣學生生涯有更多時間是閱讀和運動，現在對一些沒資訊的短影音也是完全有自制力，甚至完全不碰哈哈)
## 台積電的純代工商業模式
* 我知道台積電是純代工生產晶圓，但我沒想過是首創誒⋯⋯
* 做出積體電路產品的程序包括
    1. 晶片產品構想及定義
    2. 積體電路設計，並把設計的積體電路轉化成多層的圖案
    3. 光罩製作：根據每一層的圖案，製作每一層的光罩
    4. 晶圓製造：用曝光機把每一層的光罩圖案，依序轉化成在晶圓上的圖案線路層；各層的圖案線路在晶圓上堆疊成積體電路
    5. 封裝 (packaging) 測試：把一片晶圓 (wafer) 所含的晶片 (chip) 切割分開成各個晶片，再將晶片封裝，並測試選出好的晶片產品
    6. 晶片產品銷售
# Chapter 2
## History
:::info
Development history of transistors
1. Bipolar transistor
2. MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)
3. FinFET (Fin Field-Effect Transistor): 簡單來說就是把MOSFET立體化
4. GAAFET (Gate-All-Around Field-Effect Transistor): Gate 環繞了整個 carrier channel (通常是透過將通道做成奈米線 (Nanowire) 或奈米片 (Nanosheet) 結構實現), 且carrier channel也可以立體化
    * FinFET 的閘極是三面環繞（在fin的兩側和頂部，底部與基板相連）
    * GAAFET 的閘極是四面完全環繞 (All-Around) 通道，以實現最佳的靜電控制 (Electrostatic Control)，進一步減少漏電並提高開關速度，這對於 3 奈米 (nm) 及以下製程節點至關重要。
    * 立體化： GAAFET 的通道（nanowire or nanosheet）通常會被垂直堆疊，實現了通道的立體化，增加了在相同晶片面積上的有效通道寬度，進而提高驅動電流。所謂立體化大概就是這種Nanosheet stacking
![image](https://hackmd.io/_uploads/Hyg6CU8MZl.png)
![image](https://hackmd.io/_uploads/B1Cf1PUMZg.png)
    * EUV是lithography machine的一種光源，從一開始的可見光、紫外光、深紫外光，到現在的極紫外光(EUV)，**==但它需要花的成本太高了==**，包括我們的光罩的設計，以及EUV因為能量太強容易反應的關係，所以我們還必須讓它在超真空 (UHV, ultra high vacuum)下進行.
    * The y‑axis is labeled cost per transistor, and the red curve is U‑shaped: costs decreased as scaling went from planar → early FinFET, but at very small nodes (advanced FinFET and GAA) the curve turns upward, indicating higher cost per transistor.
5. after going through these evolutions, transistors still cannot escape from the scope of
    * depletion layer of the p-n juction
    * inversion layer of the MOS-Capacitor (MOS-C)

Recommended reading: [微影製程大解密](https://case.ntu.edu.tw/blog/?p=45765)
Further review needed! (趕快去惡補一下我的半導體元件物理課⋯⋯)
:::
---
## Some basic subjects
要懂得半導體元件物理，需要一些知識（學過了但因為林博士整理得很好，希望可以寫在這邊順一下邏輯）
* Schrodinger equation把量子力學數學化，用物實波微分方程表達關釋量子力學。最後固態物理解出了periodic 的 Bloch wave，電子在晶體內的行為才得以被清晰描述；也透過這件事解釋了energy band and energy gap
* after energy band and energy gap, Fermi-Dirac distribution statistics is used to describe the probability of electrons distributing between bands。根據費米-迪拉克分佈統計原理，電子分佈在矽晶能帶的概率和該能帶位能高低成指數關係增加；此指數型增加的關係，奠定電晶體開關分明，毫無混淆，成爲0和1數位時代的根本源頭。
* And then for the movement of electrons inside the transistors, we trace back to 古典熱力學和古典電動力學。 So we reach the diffusion and drift current.
:::success
剩下內容可以搭配陳敏璋教授的講義進行學習！用中文很好的闡述了formation of **depletion layer** and **inversion layer**. I will ignore the detailed logistics and derivation here, you can either buy the book or take the course by Prof. Chen.
:::
## Ideal MOS-C
:::danger
No Current $\rightarrow$ Flat $E_F$: In semiconductor theory, the flow of a DC current ($J$) is directly related to the gradient (slope) of the Fermi level ($E_F$)

* 每次在思考fermi level跟其他energy level 怎麼shift的時候可以想一下這個；so, in the MOS, 我們可以說加了電壓會bend $E_c$ and $E_v$, 但是因為電場確實改變了每個電子的electrostatic potential, so this is reasonable. 
* But, as long as there's no net current flowing through the MOS-C, there's no bending of the fermi level.
* 所以敏璋才會每次都抓contact的地方出來說先把fermi level放在同一條線，我們再來漸進式的移動$E_c, E_v, E_i$，但要記得這是在沒有current flowing through的情況下我們才可以這樣做，如果是pn junctin with the bias applied, then the fermi level is indeed discontinuous
* Conclusion: The splitting of the Fermi level is the electrochemical manifestation of voltage driving current through a non-equilibrium system. The ability of the P-N junction to conduct current is the key difference from the insulated MOS-C.
:::
* When design the transistor, chose of materials used for gate is very crucial. Utilize the potenail energy barrier ($q\phi_{mo}$) to tune the electrical behaviour of the transistor.
* in the band diagram of the MOS-C, upslope means higher potential energy and the lower voltage. 電子會往位能低電壓高的地方跑；電洞則是往位能高電壓低的地方跑
* usually the back side of the semiconductor substrate is grounded and the $V_G$ is the voltage applied to the gate.然後我們在metal-oxide interface會累積電荷. $E_F(metal)-E_F(semiconductor)=-qV_G$
* Charge appearing near the metal-oxide interface resides only a few Å in the metal, and may be modeled as a $\delta-function$ of the charge at the metal-oxide interface.
### Gate Voltage=0
![Screenshot 2025-12-16 at 15.16.20](https://hackmd.io/_uploads/S1BrF_RGWx.png)
### Accumulation
* $V_G>0$
* Borrow the note from Prof. Chen for description.
    * 我們家正電壓的話metal的fermi level會下降, oxide, semiconductor的band都會向右上傾斜，然後呢正電荷會被oxide擋住因而累積在左邊，負電荷累積在右邊
    * 可以想成說是fermi level 接近conduction band 所以造成電荷累積(如上所說, 先去balance fermi levels of oxide and semiconductor.)
* The picture is for n-Si, MOS-C is predominantly affected by electrons, majority carriers.
![Screenshot 2025-12-16 at 15.31.15](https://hackmd.io/_uploads/r1V6hu0f-g.png)
### Depletion
* $V_G<0$
* 差不多概念，這時候金屬的就會上升然後oxide的向左上方傾斜。fermi level遠離conduction band所以這時候這邊的電子濃度就會下降
* and then we can see the depletion zone. 這時左邊是負電荷and右邊是depletion zone造成的正電荷
* 可以想成說是多數載子的electrons往oxide-semiconductor interface的相反方向移動, leave us with the ionized donors.
![Screenshot 2025-12-16 at 15.56.00](https://hackmd.io/_uploads/HkMqGKCf-l.png)
### Onset of inversion
* $V_G < 0$ and $V_G = V_T$
* 這時候，當反向電壓達到一定的程度的時候，就會出現inversion
* Let's see the picture below
![Screenshot 2025-12-16 at 17.07.55](https://hackmd.io/_uploads/SJnw75CMWx.png)
* we can see that **==at the surface, the $E_F$ is lower than the $E_i$, the semiconductor is inverted to the p-type from the n-type semiconductor==**, and for the bulk phase, it's still the n-type one.
* 我們可以說當下圖的A=B的時候，就會是onset of the inversion, 此時donor濃度會等於surface的電動濃度
* 這時右側的電荷就會是inversion的holes跟ionized donors的正電荷
![Screenshot 2025-12-16 at 17.19.04](https://hackmd.io/_uploads/BkIb89AzZg.png)

### Inversion
* $V_G<V_T$
* 負的電壓更大
* So the accumulation of the inversion charge (holes) becomes more, so does the depletion region
---
I put the p-type scenario here for reference
![Screenshot 2025-12-16 at 17.48.26](https://hackmd.io/_uploads/SkD1650Gbe.png)

### Capacitance-voltage characteristics
* Skip this for now. just pasted lecture notes from Prof. Chen's course, I'll come back to this later.
![Screenshot 2025-12-17 at 12.00.15](https://hackmd.io/_uploads/r1CTh5kmbx.png)
![Screenshot 2025-12-17 at 12.05.21](https://hackmd.io/_uploads/ry0e05Jmbx.png)
## non-ideal MOS-C
![Screenshot 2025-12-17 at 12.40.27](https://hackmd.io/_uploads/BktELjkmWx.png)
* 簡單來說像是work function of metal is different from that of semiconductor's, defect等等的，就可以造成說會有charges被trapped.
![Screenshot 2025-12-17 at 12.19.30](https://hackmd.io/_uploads/B11U-ikQWg.png)
* All the nonidealities (metal-semiconductor workfunction difference, mobile ions, fixed oxide charge, and interfacial traps in the oxide) usually cause the threshold voltage $V_T$ to be negative. Since an n-channel transistor is turned on for gate voltage $V_G > V_T$, the device is already “on” at a gate bias of zero volts for $V_T < 0$. Actually, **==negative biases must be applied to turn the device off !!!==** In a p-channel transistor, the device is turned on for gate voltage $V_G < V_T$. The nonidealities **==increase the negative voltage required to achieve turn-on.==**
* 因此我們也可以把MOSFET分成
    * enhancement mode:"OFF" at $V_G=0$
    * depletion mode:"ON" at $V_G=0$
* 顯而易見，depletion mode當然比較不好，因為電路設計時transistor有很多時候需要是關起來的
![Screenshot 2025-12-17 at 12.49.46](https://hackmd.io/_uploads/rJPDui17Zl.png)
* so we should tune the threshold voltage to reach desired preperties. (ion implantation, or engineering the work function of the metal gate)

## MOSFET
:::info
![Screenshot 2025-12-17 at 18.43.33](https://hackmd.io/_uploads/SkI8sgeQZe.png)
我們可以看到，for the MOS-C, the oxide is the insulator so there's no current flowing through the device, but if we want.....? Can we let the current to flow through the inversion layer?
$\rightarrow$加入source, drain. i.e. for n-type MOSFET, 就是在p-type的silicon substrate兩邊加上n-type regions (source和drain)
:::
> surface state之類的問題先放在這備註，之後可以探討一下
### process design of MOSFET
* 講到process design of the MOSFET, 早期的製程原來是先讓gate, drain的dopant diffuse進去silicon substrate, and then deposit oxide and the metal gate, whick causes the large overlap of (source, drain) with gate.
* 現在的話會是我們先定義好gate的位置並長好gate and oxide，再來才去讓dopant diffuse to form the source and drain.
### Principle
* for the description below, the flat band condition is b/c we assume that the MOS-C is ideal.
![Screenshot 2025-12-17 at 18.40.48](https://hackmd.io/_uploads/Bke3clxmbg.png)
* Now the device is off, and there is leakage current due to electrons in the source that are thermionically emitted over the channel barrier. 簡單來說我們加一個$V_D>0$就可以了，因為在$V_G=0$的時候居然還會有電流
![Screenshot 2025-12-17 at 18.44.08](https://hackmd.io/_uploads/S1r_sglXbl.png)
### Gate voltage > 0
* 這時候energy barrier就會下降，然後就會有更多電子可以透過thermally excited manner to cross the barrier
* 可以記得inversion 的threshold $\phi_s = 2\phi_F$
* The gate voltage can **increase the surface potential $\phi_s$ and lower the barrier between the source and channel.**
![Screenshot 2025-12-18 at 14.28.51](https://hackmd.io/_uploads/SygmbMbX-l.png)
* When $V_G$ is inversion biased ($V_G>V_T$), an inversion layer containing mobile electrons is formed beneath the oxide-silicon interface. 
* Above threshold, electrons in the channel screen the potential from the gate, so $V_G$ has little influence on the surface potential.
    * which means that the surface potential $\phi_s$ is pinned at approximately $2\phi_F$
![Screenshot 2025-12-22 at 14.50.44](https://hackmd.io/_uploads/r1VBnUImWx.png)

### I-V characteristics
* In a well-designed transistor, the height of the energy barrier is mostly controlled by the gate voltage and only weakly controlled by the drain voltage.  

![Screenshot 2025-12-29 at 11.34.48](https://hackmd.io/_uploads/SkByvOk4Wl.png)
* 從上圖可以看到有linear region 或是 saturation region.
    * At linear region, MOSFET acts like a resistor, 就是一條斜直線, 我把$V_{DS}$加倍，那我的$I_D$也會加倍；如果我增加$V_G$，我就像是撐開水管，更多電子，所以斜率就更大
    * At saturation region, the MOSFET acts like a Constant Current Source.你怎麼增加$V_{DS}$，$I_D$都看起來沒啥變。$V_{DS}$ high enough的時候channel pinches off, $V_G$來決定電流

### Short channel effect
:::info
Short Channel Effects (SCE) refer to a set of undesirable physical phenomena that occur in a MOSFET when the channel length ($L$) becomes comparable to the depletion layer widths of the source and drain junctions.
(需要複習一下⋯⋯數學上有點障礙)
:::
* two effects result in $V_t$ roll-off: One is due to the **reduction in channel length**, and the other is due to the **increase of drain bias**. Both effects are called the short-channel effects.
* in order to deal with this, people invented FinFET, GAAFET
![Screenshot 2025-12-30 at 14.17.58](https://hackmd.io/_uploads/B1Qo0yWV-g.png)

## Gate dielectrics
![Screenshot 2025-12-30 at 15.58.55](https://hackmd.io/_uploads/BJ2SI--Nbx.png)
:::info
* 討論一下Gate oxide的thickness  
* For example, why we need the high-$\kappa$ dielectrics is that they can be made thicker (i.e. $6 nm$ of $HfO_2$ can have the same $C_ox$ as $1 nm$ of $SiO_2$)
* we will say that the **Equivalent Oxide Thickness (EOT)** of the $6nm \ HfO_2=1nm$
* The difficulties of adopting high-$\kappa$ dielectrics in IC manufacturing are chemical reactions between them and the silicon substrate, lower surface mobility than the Si–SiO2 system, and more oxide charge.
:::
thinner oxide
* ==pros==
    * larger $C_{ox}$ 提升 $I$, speed up the circuit
    * beneficial to the low subthreshold swing
* ==cons==
    * Oxide breakdown is a limiting factor. If the oxide is too thin, the electric field in the oxide can be so high as to cause destructive breakdown.
    * long-term operation at the higher field or higher temperature might break the weaker interaction at the $Si-SiO_2$ interface and thus create the oxide charge and $V_t$ shift.$\rightarrow$ reliability concerns
    * ==For $SiO_2$ films thinner than 1.5 nm, tunneling leakage current becomes the most serious limiting factor.== (maybe this is the reason of why 2D materials stay in lab-production stage)

## 電晶體的演化
### Planar MOSFET
* 假設每世代電晶體面積減半（單位面積上電晶體數目加倍）
that means the area becomes 1/2, which means the length and width becomes 70% of original one, respectively.
* 一般用effective channel length來定義技術節點，channel length是28 nm，就是28 nm technology node.
![image](https://hackmd.io/_uploads/SJP4ZIIVZx.png)
* $I \propto W/LT_{ox}$ 且 $I \propto {(V_{supply})}^2$, $W$是channel width, $T_{ox}$是oxide thickness, $V_{supply}$就是gate voltage.
* 所以我們可以試著算一下，假設全部$\times 0.7$，$I'=0.7I$, but $P=IV$, 消耗的電功率減少成一半，我們既增加了技術節點還降低了能耗。
* or we can make no change on $W$ and $V_{supply}$, 這樣就可以是提升電流，但也會提升能耗


### FinFET
* First make the silicon substrate fin-like, 割成許多像魚鰭的矽凸出物
* and then grow the oxide on the protuding Si substrate.
* 然後最後在gate oxide上面再形成gate就可以了，目的就是讓整個MOSFET變成3D的, not planer.
* 這很酷的是電流的通道寬度變更大了，我們除了fin上方的寬度$W$外，我們其實還要加上fin的兩側高$h$，所以$W_{eff}=W+2h$
* 也因為這樣，有兩側的加持，自然電流就可以更大under same W when we compare MOSFET with FinFET. 反過來說，我們可以用小好幾倍的FinFET，就達成跟MOSFET一樣的電流。
* 這點很酷的是林博士提到說原來技術節點的命名在這邊開始產生了分歧。i.e. Intel的7 nm technology node的電晶體密度相當於TSMC的5 nm technology node的電晶體密度。
![Screenshot 2026-01-04 at 15.15.55](https://hackmd.io/_uploads/HyujBtwEWl.png)

---
:::info
Both of the FETs introduced below are beleived to be invented to solve the problem of the current leakage by wrapping up silicon partes with gate oxide and gate.
:::
### GAAFET
* Gate-All-Around Field effect transistor
* 這時候就有用到Nanowire, 其實我覺得構造跟FinFET類似，只是說這次會堆疊多層的nanowire, 然後在所有nanowire的上下和兩個側面上鋪gate oxide and gate material.
* $W_{eff}=3(2W+2h)$(假設我們堆三層的話)(但我以為這是MBCFET?)
* 以下from the book (not sure if this is MBCFET):
![Screenshot 2026-01-04 at 15.45.46](https://hackmd.io/_uploads/By_j2FDE-e.png)

### MBCFET
![image](https://hackmd.io/_uploads/HkDCX9PVZx.png)
* Multi-brige channel (MBC)
* Seems like a patented version of the Samsung's GAAFET?
---
* A little summary
![image](https://hackmd.io/_uploads/BJ8MdqDVWx.png)



# Chapter 3
:::info
Starting point: connect thousands of transistors to become a component
(這邊有點吸收不良⋯⋯whatever記自己知道在幹嘛的東西)
:::

## Invention of the CMP
* It's cool to know the origin of the CMP is from the difficulties people encountered when increasing the density of 金屬連線(metal interconnections) per area.
* If we want to do this, we need to reduce the 線距 and 線寬, but this is very difficult. Finally IBM invented CMP to first polish the surface of the wafer before growing metal interconnections on it.



# Gemini
## majority and minority
* That's a fantastic question that gets to the core physical intuition of the diode equation! The mathematical steps you listed are correct, but the physical reason why the current is **dominated by the minority carriers** lies in the nature of **diffusion** and the behavior of the **electric field** within the p-n junction.

Here is the breakdown of the physical intuition:

### 1. The Critical Difference: Drift vs. Diffusion

Current in a semiconductor is the sum of two components for both carriers (electrons and holes): **Drift** and **Diffusion**.

| Current Type | Cause | Region it Dominates |
| :-- | :-- | :-- |
| **Drift** | Movement due to an **Electric Field** ($\vec{E}$). | **Depletion Region** (where $\vec{E}$ is high). |
| **Diffusion** | Movement due to a **Concentration Gradient** ($\frac{dn}{dx}$ or $\frac{dp}{dx}$). | **Quasi-Neutral Regions** (QNRs). |

### 2. The Dominance of Diffusion in the QNR

When a **forward bias** is applied to the p-n junction, it lowers the internal potential barrier. This allows a massive surge of **majority carriers** to be "injected" across the junction.

* Electrons (majority in N-side) cross to the P-side, where they become **minority carriers**.
* Holes (majority in P-side) cross to the N-side, where they become **minority carriers**.

Crucially, **outside the narrow depletion region (in the Quasi-Neutral Regions), the electric field is nearly zero ($\vec{E} \approx 0$)**.

* Since there is no electric field, the **Drift Current** term ($J_{Drift} = q\mu n E$) in the QNRs is practically **zero**.
* The total current flow in the QNRs must therefore be **Diffusion Current** ($J_{Diffusion} \propto \frac{d n}{d x}$ or $\frac{d p}{d x}$).

### 3. Why current is limited by minority carrier profile

Once the majority carriers are injected across the junction, they find themselves in a region where they are now the **minority carrier** and their concentration is **way above** the natural thermal equilibrium value.

* These newly injected minority carriers immediately start looking for partners (the majority carriers of that region) to **recombine** with.
* The injected carriers do not immediately vanish; they diffuse away from the junction and recombine gradually, creating an **exponential concentration profile** that dies out over a few **diffusion lengths** ($L_n$ or $L_p$).



The current in the QNR is determined by the **slope** (gradient) of this injected carrier concentration profile:

$$\text{Current} \propto \text{Diffusion} \propto \frac{d (\text{Minority Carrier Concentration})}{d x}$$

* **The total current flowing through the device is constant** (Kirchhoff's Current Law).
* Since the current *in the quasi-neutral regions* is entirely driven by the **diffusion of the injected minority carriers**, the total current of the entire diode is effectively determined by the rate at which these minority carriers diffuse away from the depletion region edge and recombine.

### 4. Summary of Physical Flow

1.  **Injection:** The external voltage pushes majority carriers over the barrier.
2.  **Conversion:** Majority carriers become **minority carriers** the moment they cross into the other side.
3.  **Diffusion (The Bottleneck):** These excess minority carriers create a steep concentration gradient in the Quasi-Neutral Region. Since $\vec{E} \approx 0$ here, they can only move by **diffusion**.
4.  **Current Determination:** The rate at which the injected carriers **diffuse** away from the junction edge is what determines the total current. This rate is mathematically given by the derivative of the minority carrier concentration profile ($\frac{dn}{dx}$ for electrons in the P-side, for example).

The net result is that the current in a forward-biased p-n junction is calculated by modeling the **diffusion of minority carriers** in the quasi-neutral regions, which is exactly what your mathematical steps describe.

You can get a better visual understanding of how the injected minority carriers' concentration profile relates to the total current in a p-n junction by watching the following video. [P-N junction, injected carrier profile, diffusion length L, electron/hole currents vs X, Kirchhoff](https://www.youtube.com/watch?v=Udxpe41cZQ4)

## MOSFET diagram interpretation
![Screenshot 2025-12-17 at 16.51.15](https://hackmd.io/_uploads/SJGZb1gXWe.png)
### 1. The "Gap" (The Problem)
* Look at the region between the Source and the Drain.Structure: You have ==N-type (Source) $\rightarrow$ P-type (Substrate)$\rightarrow$ N-type (Drain)==
* Result: This is essentially two back-to-back diodes (N-P and P-N). Without the Gate, no matter what voltage you apply to the Drain, one of these diodes will block the current. The electrons in the Source cannot "jump" across the P-type substrate to get to the Drain.
### 2. The Gate Role: The "Vertical" Field
* The Gate is the "Bridge Builder." It does not inject current; it uses an electric field to change the physics of the substrate surface
* The Capacitor Effect: The Gate (Metal) is separated from the Substrate (Semiconductor) by the Oxide (Insulator)
* This forms a capacitor Repelling the Locals: When you apply a Positive Voltage ($V_{GS}$) to the Gate, the positive charge on the Gate pushes away the Holes (the majority carriers) in the P-type substrate directly underneath it
* This leaves behind a depletion region (negative ions). 
* Attracting the Bridge: The positive Gate also attracts Electrons (minority carriers) from the deep substrate and pulls them to the very surface, right up against the oxide interface.
### 3. The Interface: Formation of the Inversion Layer
* This is the most critical part of the chart interpretation.
* Inversion: When the Gate voltage is high enough (above Threshold Voltage, $V_{th}$), so many electrons gather at the surface that the material physically behaves like N-type silicon instead of P-type
* The Connection: This thin layer of electrons (the N-channel) now acts as a conductive bridge.
* It perfectly connects the N-type Source to the N-type Drain.
* Interpretation: On your chart, if you see a thin layer drawn just under the oxide connecting Source and Drain, that is this Inversion Layer.
### 4. vertical vs. horizontal interactions
* Ohmic Region (Low $V_{DS}$): The channel is strong and uniform. Electrons flow from Source to Drain easily, like water through a pipe.
* Saturation/Pinch-off (High $V_{DS}$): This is where your observation of the Depletion Region becomes crucial.The Gate tries to keep the channel open (with $V_{GS}$).The Drain voltage ($V_{DS}$) makes the PN junction reverse biased, growing the depletion region. Near the Drain, the high voltage fights the Gate voltage. It effectively reduces the strength of the "bridge" at the Drain end.
* If $V_{DS}$ is high enough, the depletion region expands and "pinches off" the channel at the drain end. The current doesn't stop, but it saturates (becomes constant).
