---
title: 'RISC-V Note'
disqus: hackmd
---
---
**Update:** 112/7/26
---
[TOC]
# Basic
## [OpenHW GitHub Repository](https://github.com/openhwgroup)
<img src="https://www.openhwgroup.org/images/openhw-landscape.png" width="418px" height="103px" /> <img src="https://www.openhwgroup.org/images/core-v-portrait.png" align="right" width="150px" height="120px"/>
# About OpenHW Group
OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.
Please see our [website](https://www.openhwgroup.org/) for membership information, latest news, and further resources.
# OpenHW Group CORE-V Family of Open-Source RISC-V Cores
Below is the CORE-V Roadmap of Application class and Embedded class cores. Please see [core-v-cores repo](https://github.com/openhwgroup/core-v-cores) for roadmap details.
<img src="https://github.com/openhwgroup/core-v-cores/blob/master/CV-CORES-Roadmap_2023-03-14.png" align="center" />
# Project Repositories Table of Contents
| Working Group | Repo | Description |
| -------------------- | -------------------- | -------------------- |
| Cores TG | [Core-v-cores roadmap](https://github.com/openhwgroup/core-v-cores) | |
| | [CTG meetings and minutes](https://github.com/openhwgroup/programs/tree/master/TGs/cores-task-group)| |
| | [CVA6](https://github.com/openhwgroup/cva6) | 6-stage, application-class core |
| | [CVA5](https://github.com/openhwgroup/cva5) | 5-stage, FPGA-optimized application-class core |
| | [CVW](https://github.com/openhwgroup/cvw) | 5-stage, application-class core with education focus |
| | [CV32E40P](https://github.com/openhwgroup/cv32e40p) | 4-stage, embedded-class core implementing PULP extensions |
| | [CV32E40S](https://github.com/openhwgroup/cv32e40s) | 4-stage, embedded-class core with security focus |
| | [CV32E40X](https://github.com/openhwgroup/cv32e40x) | 4-stage, embedded-class core supporting X-Interface |
| | [CV32E41P](https://github.com/openhwgroup/cv32e41p) | 4-stage, embedded-class core prototyping Zfinx and Zce |
| | [CV32E20](https://github.com/openhwgroup/cve2) | 2-stage, embedded-class microcontroller core and core complex |
| | [CV-HPDCACHE](https://github.com/openhwgroup/cv-hpdcache) | High performance L1 Data Cache |
| Verification TG | [VTG meetings and minutes](https://github.com/openhwgroup/programs/tree/master/TGs/verification-task-group)| |
| | [CORE-V Verif](https://github.com/openhwgroup/core-v-verif) | Common test bench for OpenHW Cores |
| | [FORCE RISC-V](https://github.com/openhwgroup/force-riscv) | Advanced RISC-V instruction set generator |
| | [ARVM](https://github.com/openhwgroup/advanced-riscv-verification-methodologies) | Advanced RISC-V Verification Methodologies |
| Software TG | [SWTG meetings and minutes](https://github.com/openhwgroup/core-v-sw) | |
| | [CORE-V GNU Tools](https://github.com/openhwgroup/corev-gcc) | GNU Tools Project for embedded-class CORE-V cores |
| | [CORE-V LLVM](https://github.com/openhwgroup/corev-llvm-project) | LLVM Tools Project for embedded-class CORE-V cores |
| | [CORE-V FreeRTOS Kernel](https://github.com/openhwgroup/core-v-freertos-kernel) | FreeRTOS Kernel for embedded-class CORE-V cores |
| | [CORE-V FreeRTOS](https://github.com/openhwgroup/core-v-freertos) | FreeRTOS for embedded-class CORE-V cores |
| | [CORE-V QEMU](https://github.com/openhwgroup/corev-qemu) | QEMU emulator for CORE-V-MCU |
| | [CORE-V SDK](https://github.com/openhwgroup/core-v-sdk) | SDK and IDE for embedded-class CORE-V cores |
| Hardware TG | [HWTG meetings and minutes](https://github.com/openhwgroup/programs/tree/master/TGs/hardware-task-group) | |
| | [CORE-V-MCU](https://github.com/openhwgroup/core-v-mcu) | ASIC and FPGA MCU implementation of CV32E40P |
| | [CORE-V-MCU-DEVKIT](https://github.com/openhwgroup/core-v-mcu-devkit) | Devkit for CORE-V-MCU |
| | [CORE-V-POLARA-APU](https://github.com/openhwgroup/core-v-polara-apu) | Multicore CVA6/CVVEC ASIC with OpenPiton |
| Technical Working Group | [OpenHW project dashboard](https://github.com/openhwgroup/programs/tree/master/dashboard) | |
| | [Project Description Folders](https://github.com/openhwgroup/programs/tree/master/Project-Descriptions-and-Plans) | |
| | [OpenHW Project process and templates](https://github.com/openhwgroup/programs/tree/master/process) | |
---
## [CV32E40P User Manual](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/)
### Introduction
CV32E40P is a 4-stage in-order 32-bit RISC-V processor core. The ISA of CV32E40P has been extended to support multiple additional instructions including hardware loops, post-increment load and store instructions, additional ALU instructions and SIMD instructions that are not part of the standard RISC-V ISA. The following blockdiagram shows the top level with the core and the FPU.
---
# Quick Start
* Setup environment.
```gherkin=
source /imdlnas/m2022/jack/setup.sh
```
* Copy source code.
```gherkin=
cp -r /imdlnas/m2022/jack/riscv/reLeNet_riscv .
```
* Goto **"01_RTL"** and put your **"C Code"** in **"src_code"**. The directory hierarchy is as follows.
```gherkin=
/ reLeNet_riscv
| +- 00_TESTBED # Testbed & Pattern
| +- 01_RTL # Pre-sim
| +- Makefile # Include command script
| +- TESTBED.sv # Soft link to ../00_TESTBED/TESTBED.sv
| +- design # RTL code
| +- src_code # C code & Compiled code
+- 02_SYN # Synthesis
+- 03_GATE # Gate-sim
...
others # Don't care
...
```
* (01_RTL) Compile source code. The extension **".c"** is not required.
```gherkin=
# Template
make compile src=<path_to_src_code>
# Example w/ random system stall
make compile_stall src=helloworld
# Example w/o random system stall
make compile src=helloworld
```
* (01_RTL) After compilation, 2 files are .generated under **01_RTL**.
```gherkin=
# Executable and Linkable Format for RISCV
helloworld.elf
# Instruction in hexadecimal
helloworld.hex
```
* (01_RTL) Run simulation.
```gherkin=
# Template
make sim src=<path_to_src_code>
# Example
make sim src=helloworld
```
* (01_RTL) Cleanup is optional.
```gherkin=
# Clean up everything except "INCA_libs"
make clean
# Clean up everythig
make clean_all
```
---
# TODO (Freeze)
* **(7/27) Week 1:** Warmup
* Read and familiarize with the CV32E40P User Manual.
* Run and trace the code, including:
* Synthesizable RTL in **01_RTL/design**
* Testbed and behavior RTL in **00_TESTBED**
* C code and Compiled code in **01_RTL/*** and **01_RTL/src**
* **(Optional)** Write and use your own C code.
* **(Weekly Meeting)** <font color="#f00">A briefly introduction and its work flow.</font>
* **(8/3) Week 2:** RISC-V Instructions Usage
* Survey how to use the compiled instruction to control the **"Reconficurable LeNet Accelerator"** **(reLeNet)**.
* The specification document of reLeNet is located at **root**.
* Each type of LeNet requires 7 instructions (data is in **00_TESTBED/data**):
| | TYPE | RELU | H | R | C | K | P | SCALE | Conf. bits (HEX) |
|:----:|:----:|:----:|:---:|:---:|:---:|:---:|:---:|:---------:|:----------------:|
| CONV | 00 | 1 | 101 | 10 | 000 | 000 | 0 | 000111011 | 0036003B |
| MAX | 01 | 0 | 100 | 00 | 001 | 000 | 0 | 000000000 | 00502000 |
| CONV | 00 | 1 | 011 | 10 | 001 | 010 | 0 | 001111111 | 002E287F |
| MAX | 01 | 0 | 010 | 00 | 010 | 010 | 0 | 000000000 | 00484800 |
| CONV | 00 | 1 | 001 | 10 | 010 | 100 | 0 | 010001010 | 0026508A |
| FC | 10 | 1 | 000 | 00 | 100 | 011 | 0 | 100010010 | 00A08D12 |
| FC | 10 | 0 | 000 | 00 | 011 | 001 | 0 | 001011110 | 0080645E |
* RISC-V instructions are only available when both **ready** and **active** are logic high.
* **(8/10) Week 3:** RISC-V Memory Interface Usage
* Explore how to use RISC-V Memory Interface
* Pseudo DRAM -> SRAM
* SRAM -> Pseudo DRAM
* **(8/17) Week 4:** Synthesis & Gate simulation
* Synthesize reLeNet along with RISC-V core.
* The script is ready, but there might be some bugs or non-rigorous constraints.
* **(8/24) Week 5:** (Optional) APR & Post simulation
* Simulate tape-out flow along with RISC-V core.
* Record related data (area, timing, ...).
* Function verification.
---
```mermaid
gantt
axisFormat %-m/%-d
title Timeline
%%excludes weekends
section Action
Warmup : crit, active, a1, 7/27, 2w
RISC-V Instructions Usage : active, a2, 8/3, 2w
RISC-V Memory Interface Usage : active, a3, 8/10, 3w
Synthesis & Gate simulation : active, a4, 8/17, 3w
(Optional) APR & Post simulation : active, a5, 8/24, 2w
section Milestone
7/27: active, milestone, 7/27, 1d
section Deadline
9/7: crit, milestone, 9/7, 1d
```
# Action Item
```mermaid
gantt
axisFormat %-m/%-d
title Timeline
%%excludes weekends
section Milestone
9/27: active, milestone, 9/27, 1d
section Action
Spec (Critical I/O) : crit, active, a1, 9/27, 8d
RISC-V Behavior Trace : active, a2, 9/27, 2w
RTL (Shift Reg/MUX/Removal) : active, a3, 9/27, 2w
RISC-V Synthesis : active, a4, 10/4, 2w
RISC-V APR : active, a5, 10/4, 2w
RISC-V Freeze : crit, a6, 10/17, 1d
Chip Integration : active, a7, 10/4, 2w
Chip Mesh / Dummy : active, a8, 10/11, 2w
Chip Freeze : crit, a9, 10/24, 1d
Final Check : crit, a10, 10/24, 1w
section Testmodes
One Way Ticket to the Blues : done, a1, 9/27, 3w
Testmode Freeze : crit, a9, 10/17, 1d
section Deadline
(10/25~10/31) 1st gds: crit, milestone, 10/25, 1d
(11/1~11/7) Final gds: crit, milestone, 11/7, 1d
```
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