## Adder Designs Using Verilog Structural, Dataflow, and Behavioral Modeling

> GitHub：[HDL_hw1](https://github.com/SuNsHiNe-75/HDL_hw1)

It mainly covers the following tasks:
- Designing a 32-bit adder using different Verilog modeling methods (Structural Modeling, Dataflow Modeling, Behavioral Modeling).
- Storing outputs in registers.
- Pre/post-synthesis simulation (using **Ncverilog** for pre/post-simulation, using **Design Compiler** for synthesis).
- Comparison of synthesis results.