## Adder/Subtractor/Multiplier Designs: Non-Pipelined versus Pipelined

> GitHub：[HDL_hw2](https://github.com/SuNsHiNe-75/HDL_hw2)

It mainly covers the following tasks:
- Adder/Subtractor/Multiplier Designs: **Non-Pipelined**
- RTL Simulation of Non-Pipelined Design
- Logic Synthesis with Synopsys Design Compiler
- Adder/Subtractor/Multiplier Designs: **Pipelined**
- Simulation of the Pipelined Design
- Logic Synthesis of the Pipelined Design
- Clock Gating
- Simulation and Synthesis of Clock-Gated Pipelined Design
- PrimeTime Simulation
- Comparison
- Implementation in FPGA（using Xilinx）