# Basic Computer Organization

## Stored Program Organization

We define a stored-program digital computer is that it keeps programmed instructions, as well as data, in read-write, RAM. Here we mainly explore the Von-Neumann architecture.

### Timing Control

**Clock and Cycles**

The clock is the signal that keeps the control unit moving. Each tick from the clock results in control unit moving to the next machine cycle (next instruction). Activites on the system bus is synchronized to the system clock. These can include:

- reading from memory or I/O
- writing to I/O

**The speed of CPU is determined by clock cycle (cycles per second) measured in Hz, typically MHz and GHz.** This way we can effectively calculate how much cycles the CPU can perform under a second.

**T-State**

A complete cycle is called a T-State, measured from the falling edge of one clock pulse to the falling edge of the next clock pulse.


**Bus Cycle**

Any read/write cycle = bus cycle (machine cycle). These can include:

- memory read/write
- I/O read/write

## Instruction Cycle

This relates to the time taken by processor to execute an instruction (number of clock cycles). The processor fetches an instruction then decodes, ready to execute. This is known as the fetch-execute cycle that can be divided into:

- Fetch Instruction
- next instruction fetched from memory address stored in PC and IR
- Decode Instruction
- PC points to next instruction that will be read at the next cycle
- Read Operand Address
- executed in next clock pulse
- indirect address: read from main memory, placed into data registers
- nothing done at current clock pulse, unless it's I/O instruction or Register Instruction, operation performed at clock pulse
- Fetch Operand
- Execute Instruction
- control unit passes decoded information as a sequence of control signals to relavent function units to perform actions required by instructions
- read from register, ALU performs arithmetic calculations, writing result back to register
- if ALU is involved, sends condition back to CU, generate result to store in main memory / sent to output device
- based on condition of any feedback from ALU, PC may be updated to diff address from which the next instruction will be fetched
- Write/Store Result in Memory

## Chip Organization

We say that a Von Neumann computer model consists a shared main memory, CPU, I/O devices, registers and buses.

### Central Processing Unit (CPU)

CPU is an electronic circuitry that carries out instructions given by a computer program.

### Main Memory

Memory can be classified as:
- Random Access Memory (RAM)
- used when running the program
- cleared every reboot
- Read Only Memory (ROM)
- holds data, not cleared during reboot
- stores firmware, BIOS
- Secondary Memory
- extra data storage for permanent record
- hard disks, flash drives, etc

### I/O Devices

Input device such as keyboard, mouse, etc allows communication of information to the machine whereas output device send out information to the user which can be speakers, monitor, etc.

### Software

Software is basically parts that is visible but untouchable. It can be operating systems or programs.

### Categories of Terminologies


## I/O and Interrupt

We say that an interrupt is a method of **temporarily halting programs during execution to allow peripherals to access the microprocessor.** The microprocessor responds to the interrupt via **Interrupt Service Routine (ISR)**, a short program to **instruct it on how to handle the interrupt.**

This is known as a hardware interrupt. The peripheral sends a signal through a specific pin to the microprocessor. Taking the example of a 8086 microprocessor, hardware interrupts can be further categorized as non-maskable and maskable interrupt pins which are NMI and INTR, respectively.

### NMI (Non-Maskable Interrupt Pin)

- higher priority
- type 2 interrupt

Activating this pin it performs the following actions:
- completes current instruction that is in progress
- pushes flag register values onto stack
- pushes CS value and IP value of the return address onto stack
- IP loaded from contents of word location 00008H
- CS loaded from contents of next word location 0000AH
- reset interrupt flag and trap flag to 0

### INTR （Maskable Interrupt Pin)

INTR is maskable because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It shouldn't be enabled using clear interrupt flag instruction.

This is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes current instruction and sends '0' on INTA pin twice:

- first '0': INTA informs external device to get ready
- second '0': microprocessor receives the 8 bit number from the programmable interrupt controller

**The following actions:**

- completes current instruction
- activates INTA output and receives interrupt type we call $X$
- flag register values, CS value and IP value of return address pushed onto stack
- IP value loaded from contents of word location $X \times 4$
- CS loaded from contents of next word location
- reset interrupt flag and trap flag to 0