# FAPI interface and nFAPI interface. What is different between them. ###### tags: `Internship 2nd level` :::success **Goal:** - Understanding of the procedures involved in FAPI. - Figured it out of the procedures involved in nFAPI. - Clear understanding of differenties between them. **Resources:** - [FAPI interface](https://www.techplayon.com/5g-fapi-femtocell-application-programming-interface/) - [nFAPI interface](https://hackmd.io/69yckFNZS_i9vogWpyRISQ?view) - [FAPI vs nFAPI](https://scf.io/en/documents/082_-_nFAPI_and_FAPI_specifications.php) ::: ## FAPI interface FAPI is an interface, which originally meant Femtocell Application Programming Interface defines the interface between MAC-Layer#2 and PHY – Layer#1 for small cells. FAPI is specified by the Small Cell Forum and the original interface defined the interaction between a 3G MAC and PHY (SCF 048), Subsequently a version was defined between a 4G MAC and PHY (SCF 082), and recently the 5G version has been completed (SCF 222). For each wireless technology FAPI defines a set of control messages for configuring a PHY and a set of messages for exchanging data between MAC and PHY, and indicates the timing constraints of these messages. Key Pointers: FAPI means Femtocell Application Programming Interface It is an interface between MAC and PHY in Small Cells FAPI specification are managed by Small Cell Forum FAPI specification has defined two Logical interface P5 and P7 The PHY control plane message are transferred over P5 interface The PHY data-plane messages are transferred over P7 interface FAPI Architecture The architecture of FAPI is shown in figure below. FAPI is defined between one instance of MAC and one instance of PHY. In scenarios such as CA there will be multiple instances of FAPI, one per carrier. There are two types of PHY configuration messages are defined by the logical interface as P5 and P7. P5 Logical Interface is for PHY control configuration which is semi-static and is being generated by a PHY control entity. ![](https://imgur.com/utA05Gt.png) The P7 logical interface is for PHY data plane messages, P7 interface data configuration is generated once per slot and consists of following: Slot configuration messages, which include information required by the PHY to encode and decode data Downlink data messages to transfer MAC PDUs to the PHY. Uplink data messages to transfer MAC PDUs, Uplink Control Information ,Sounding Reference Signal and RACH PDUs from the PHY P5 – Control Configuration Procedures The Control configuration procedures supported by the L1 FAPI over P5 interface are listed below: Initialization Termination Restart Reset Error notification These procedures will move the PHY layer through the IDLE, CONFIGURED and RUNNING states P7 – Data Plane Configuration Procedures The P7 – Data plance configuration procuedres serve two purposes for subframes procedures. Firstly, they are used to control the DL and UL frame structures. Secondly, they are used to transfer the subframe data between the L2/L3 software and PHY. The procedures supported by the L1 FAPI over P7 interface are listed below: Transmission of a 1ms Subframe message Synchronization of SFN/SF between the L2/L3 software and PHY Transmission of the BCH transport channel Transmission of the PCH transport channel Transmission of the DLSCH transport channel and reception of ACK/NACK response Transmission of the MCH transport channel Reception of the RACH transport channel Reception of the ULSCH transport channel and transmission of ACK/NACK response Reception of the sounding reference signal Reception of CQI and RI reporting Reception of scheduling request information ## nFAPI interface. nFAPI assumed that a packet switched IP network is used to support communication between VNF and PNF components. nFAPI Procedures: 1. PNF Procedures 2. P5 PHY Procedures 3. P7 Slot Procedures 4. nFAPI Error Procedures 5. P19 Procedures 6. P19 Slot Procedures 7. P4 Procedures ## What is different between them. The nFAPI P7 interface configures the PHY instances every slot and is based on the 5G FAPI P7. Slot Signal: SLOT.indication message is not used, since the expected jitter on the fronthaul connection between VNF and PNF prevents this message from being a suitable mechanism for signalling a slot interval. Combination of the PHY Synchronization procedure and API Message Timing procedure ensures the alignment of MAC commands to air-interface slots. SFN/SL Synchronization PHY Synchronization mechanism and Delay Management mechanisms is used to maintain synchronization between PHY instances and ensure timely messaging between the VNF and PHY instances. PHY Synchronization Relates to the alignment of antenna transmission times between the PHY instances. Delay Management between VNF and PHY Ensures that P7 slot procedures to occur in a timely fashion. PHY instance expects P7 slot-based messages from VNF to reach the instance in a Receive Time Window interval, that PHY maintains to buffer and process time-critical P7 messages (DL_TTI.request, UL_TTI.request, UL_DCI.request, Tx_Data.request), to apply at their targeted slots. Receiving Windows Procedure Each PHY maintains a Receive Timing Window characterized by timing window and offset prior to the targeted slot. Delay Management Procedure Can be used to establish the timing reference differences between them as well as optionally permitting the VNF to instruct the PHY Instance to update its slot number based on the offset defined by the VNF. API Message order Same with FAPI with exception: SLOT.indication message is replaced by the Delay Management procedure. In particular, the DL_TTI.request message is expected to arrive at the PHY in the Receive Window for to the SFN/SL listed in the message. No order requirement between the DL_TTI.request and UL_TTI.request messages for a particular SFN/SL The DL_TTI.request and UL_TTI.request messages are expected to arrive at the PHY in their respective Receive Windows for to the SFN/SL listed in the message. API Message Timing The nFAPI P7 messages listed in Delay Management sent from the VNF to PNF must arrive at the PHY instance a minimum Timing offset before the slot they configure starts transmission on the air interface. If the message arrives in the allowed timing window, then the PHY instance continues normal operation for the slot. If the message is late then the PHY instance follows the procedure below.