---
title: <半導體製程導論>
image: https://i.imgur.com/zFQsuBw.png
description: 偏考試導向的重點整理啦
---

# 半導體製程導論

## 第一章
### 重點
1. 討論晶圓及製造晶圓的5個主要階段。
2. 敘述與討論晶圓製造的改進技術之3項重要趨勢。
3. 說明臨界尺寸(CD)之定義，與Moore's定律。

### 基本問題
* What is a wafer?
* How it is layered?
* Descrive the essential aspects of the 5 stages of wafer fabrication.
* State and discuss the three major trends associated with improvement in wafer fabrication.
* Explain what is a critical dimension and how Moore's law predicts future wafer fabrication improvement.

### 段落小問題

1. Why do you need silicon wafer flats?
:::spoiler **Ans here**
才能決定 type & orientation.
:::
2. What is the reason for polish grinding?
:::spoiler **Ans here**
Grinding removes saw marks and levels and cleans the specimen surface.
為了在表面(一面)做元件
:::
3. The number of transistors per chip is rapidly increasing while the chip power consumption is reducing. Why?
:::spoiler **Ans here**
密度增加transistor變小 -> 功率 & 工作頻率穩定 & consumption下降。
:::

### 內容摘錄

#### Evolution of Wafer Size
* **silicon wafer /substrate**
- **chips/die/microchip** are fabricated on it
+ its size depending on the level of integration on the chip
- wafer diameter has evolved from
+ 50mm ~ 300mm
- cost
+ drops dramatically
#### Semiconductor Trends
Customers need
1. **Faster**
2. **More reliable**
3. **Lower cost**

This induced
1. Increase chip performance (e.g. chip speed、reduced power comsumption)
* As device miniaturization proceeds, there is corrsponding reduction in power consumption
3. Increase chip reliability
* Advances in technology
4. Reduce chip cost
* Reduce size & Increase the wafer diameter
* the large market growth for semiconductor products
#### Critical Dimension(CD)(臨界尺寸)
The physical dimension of a feature on a chip is referred to as the feature size(特徵尺寸). Another term to describe feature size is circuit geometry. Of special note is the minimum feature size on a wafer, known as the critical dimension.

#### Moore's Law
Gordon Moore predicted that the number of transistors on a chip would double roughly every year.

### HW
1. Q1.6 : What is a wafer?What is a substrate? What is a die?
:::spoiler **Ans here**
簡短：==round thin crystalline disks==
成千上萬相似的chips被刻在silicon wafer上，chips的數目由wafer的種類跟尺寸決定，chips的尺寸由wafer的level of integration決定。
The chip也稱為die，the silicon wafer通常稱為substrate.
:::
2. Q1.8 : List the five major stages of IC fabrication, and give a short description.
:::spoiler **Ans here**
1. **Wafer preparation** : crystal growing -> rounding -> slicing -> polishing.
2. **Wafer fabrication** : cleaning -> layering -> patterning -> etching -> doping(添加改變導電性之物質).
3. **Test/Sort** : probing(electrically testing each die on a wafer) -> testing -> sorting of each die on the wafer.
4. **Assembly and Packaging** : The wafer is cut along scribe lines to separate each die. Metal connections are made and the chip is encapsulated.
5. **Final Test** : ensures IC passes electrical and environmental testing.
:::
3. Why are silicon wafers round?
:::spoiler **Ans here**
因為是高溫熔融silicon繞著seed慢速旋轉所提煉出來，造成ingot一開始生成就是圓的，如果切成其他形狀的晶片會浪費原料。
:::
4. What is the reason for wafer edge rounding?
:::spoiler **Ans here**
* 避免碰撞傷到晶片
* 避免切的時候因為有邊角會有碎片
* 把風險降到最低
:::

## 第二章
### 重點
1. 由能帶理論觀念定義材料的三大分類：導體、半導體、絕緣體
2. 本質矽與外質矽定義
3. 為何採用矽?(四大原因)
4. n型與p型矽

### 基本問題
* State the three classes of materials and describe each one with regards to current flow.
* Describe pure silicon and give four reasons why it is the most common semiconductor material.
* Explain doping and how the trivalent and pentavalent dopant elements make silicon a useful semiconductor material.
* Explain p-type(acceptor) silicon and n-type(donor) silicon.
### 內容摘錄
#### Three classes of materials
* Conductors
:::spoiler **details here**
Electrons readily flow throught the material as electrical current
:::
* Insulators
:::spoiler **details here**
A material that has high resistance to current flow.
:::
* Semiconductors
:::spoiler **details here**
They can function as either conductors or insulators.
:::

#### Silicon
##### Pure Silicon (intrinsic silicon)
with no contaminants or impurities (自然含有之雜質) from other substances.

##### Why Si
* Abundance of silicon (cost low)
地球組成約25%的矽，地球上含量第二豐富元素，原料具低成本優勢
* Higher melting temperature for wider processing range
矽熔點1214度高於鍺熔點937度使矽製程可採用較高溫度
* Wider temperature range of operation
矽製備的原件可正常遭做溫度範圍較大，有較佳的可靠度和應用範圍
* **Natural growth of silicon oxide**
自然生成的二氧化矽是良好的絕緣體，二氧化矽可保護下方的矽，也可於高溫下製造，具有穩定的絕緣特性，可改善相鄰元件的漏電流

##### Doped Silicon (extrinsic silicon)
* **Doping** is the process of adding small amounts of other elements to the material through a process known as *doping*
* The elements adding during doping are referred to as *dopants* or *impurities*.
* Silicon Dopants :
* p-type silicon : trivalent dopant(acceptors) atoms(e.g. boron$(\ce{B})$ are added to silicon.
* n-type silicon : pentavalent dopants(donors)(e.g. either phosphorous$(\ce{P})$, arsenic$(\ce{As})$, or antimony$(\ce{W})$) is added to pure silicon.
* 3 steps process :
1. **Deposition** : the dopant is deposited(沉積) evenly onto the surface of the wafer.
2. **Drive-in** : the wader is heated to drive the dopants into the silicon.
3. **Activation** : once inside the lattice structure(晶格結構), the dopant atoms become activated, that is, they bond with silicon atoms to become part of the overall crystal structure.

### HW
1. Q2.16 : What is the difference between intrinsic and extrinsic silicon?
:::spoiler **Ans here**

:::

## 第四章
### 重點
* 晶體結構
- 晶胞
- 非晶、多晶與單晶結構
- 晶體方向
* CZ法
* 晶圓準備流程
* 晶圓良率定義
### 基本問題
1. Explain the crystal structure and growth method for producing monocrystalline silicon.
2. Descrive the basic process steps for wafer preparation, starting from a silicon ingot and finishing with a wafer.

### 內容摘錄
#### Crystal Structure
* **Amorphous Materials**
a noncrystalline solids that lack a repetitive structure and demonstrate structural disorder at the atomic level.
* **Unit Cells**
the simplest arrangement of atoms that, when repeated in a three-dimensional framework, gives the crystal structure.
* **Polycrystal and Monocrystal Structures**
the unit cells are ==not in a regular arrangement== $\to$ *polycrystalline*.
the unit cells are neatly arranged in a ==three-dimensional, repeatable manner== $\to$ *monocrystal*.
* **Crystal Orientation**
* 晶體方向的重要性在於它決定了wafer上的silicon晶體的排序是否整齊。
* 不同的方向會影響矽的：化學、電、機械的性質。
* 定義晶體方向的坐標系：
* 各個結構上的示意圖：

#### CZ Method
The Czocharalski (CZ) growth of a silicon monocrystal 包含將熔融態SG矽轉變為固體矽的ingot(有正確晶體排列 + doped成n-type或p-type)
* Single silicon Ingot production process
- Step1: Preparation of high purity of molten silicon
- Step2: Dipping seed crystal
- Step3: Pulling the seed Upwards
* Seed: to grow the silicon ingot that is replica of the original seed crystal
* The rotating direction of seed is opposite to the rotation of crucible
* The objective of the pull process is precisely replicate the seed structure
- Two main parameters: pull rate and crystal rotation
* A goal of the crystal growth process is to have uniform, large-diameter crystals

#### Preparation of Silicon Wafers
#### Annealing&Tempering的差別
* Annealing
退火，為一種改變材料微結構且進而改變如硬度和強度等機械性質的熱處理
過程：將金屬加溫到某個高於再結晶溫度的一點並維持此溫度，再將其緩慢冷卻。
* Tempering
回火，可以去除淬火鋼內部的應力，也可以調節硬度以得到適當的強韌性
過程：把淬火鋼加熱到共析以下的適當溫度
#### Crystal Defects in Silicon
A *crystal defect* is any interruption in the repetitice nature of the unit cell crystal structure. Another term used for a crystal defect is *microdefect*
> **Define density** : the # of defects per $cm^2$ of wafer surface that may occur during processing due to all kinds of causes
>
$$\boxed{
\text{Yield} = \frac{66\,\text{good die}}{88\,\text{good die}}=75\%}
$$

### HW
1. Q4.4 : Describe an amorphous material. Why is this unacceptable for the silicon used in wafers?
:::spoiler **Ans here**
*Amorphous materials* are noncrysyalline solids that lack a repetitive structure and demonstrate structural disorder at the atomic level.
This is because many of the ==electrical and mechanical== aspects of a device occur at the atomic level in the silicon, which requires ==order and predictability== to yield repeatable results from chip to chip,
:::
2. Q4.9 : Why is it necessary to have monocrystal silicon for wafer fabrication?
:::spoiler **Ans here**
Semiconductor wafer processing requires a pure, monocrystalline silicon structure (single crystal).因為單晶結構提供理想的電性和機械特性，對wafer的製造和表現是必要的，反之如果是不允許的結構的話，將會影響到wafer的形成而出現瑕疵。
:::
3. Q4.15 : Describe the silicon seed for CZ method and how it is used?
:::spoiler **Ans here**
CZ mtd:
The CZ growth of a silicon monocrystal involves the transformation of molten SG silicon liquid into a solid silicon ingot that has the correct crystal orientation and is doped either as n-type or p-type.
Single silicon Ingot production process
- step1 : Preparation of high purity of molten silicon
- step2 : Dipping seed crystal
- step3 : Pulling the seed Upwards
:::

## 第九章
### 重點
1. 晶圓廠製造區域
* 擴散、微影、蝕刻、離子植、薄膜、研磨
2. CMOS製造步驟
* N-well形成步驟

### 內容摘錄
#### Definition of a cleanroom
* A class 1 room: the ISO standard allowing less than 2 particles greater than 0.3 microns and no particles greater than 1.0 microns per cubic meter.
|每立方公尺 允許小於2個大於0.3微米 且 不允許大於1微米 的粒子|

#### Overview of Areas in a Wafer Fab

* **Diffusion**
- 地點：the diffusion bay
- 主要工具：*high-temperature diffusion furnace*, *wet cleaning station*
- 進行高溫處理和film depositions的區域
- 送進儀器前必須先去除wafers表面汙染物和氧化層
* **Photolithography**
- 地點：the photolithography bay (黃光環境：才不會影響到光阻)
- 利用UV與白光會使光阻曝光的性質把設計好的layouts印上去
- 主要工具：the *coater/developer track*
+ **stepper** (阻擋UV光來做出三維立體結構):
先將wafer依die上面鍍的鉻膜上刻的圖對齊。然後stepper會對小區域曝光再移動到下個區域，此過程會重複直到把整個die的圖曝光完
* **Etch**
- 會對晶圓區造成永久性光阻的移除且無法復原
- 主要工具：*plasma etcher*, *the plasma resist stripper*, and *the wet cleaning station*
- 原理：把離子化的氣體分子利用電廠去驅動它們移除一些不要的光阻
* **Ion Implant**
- 工具：*ion implanter*
- 攜帶所需dopant的氣體：arsenic$\ce{(As)}$, phosphorus$\ce{(P)}$, boron$\ce{(B)}$
- 會用到離子植入機，先輸進氣體把它離子化形成電漿，再通**高壓電和磁場**去控制和加速粒子，最後轟擊到晶圓裡面。
* **Thin Films**
- 地點：the *thin films bay*
- 工具：*chemical vapor deposition (CVD)* and *metal sputtering tools (PVD)*
- 經過一些不同的工程步驟，沉積介電與金屬層
* **Polish**
- 工具：CMP(chemical mechanical planarization)
- CMP用結合化學蝕刻和機械研磨去除表面不平整的表面
- 把頂層表面平面化
#### CMOS Manufacturing Steps
#### n-well Formation

1. **Epitaxual growth 外延生長**
A very pure silicon surface of the same crystal structure as the substrate wafer, yet retain control over the doping type or concentration
* the base wafer is used as a seed crystal to grow a thin layer of silicon on the wafer
* The substrate wafer is monocrystal, the epitaxial layer is monocrystal
- the dopant of the epitaxial layer can be n-type or p-type and is independent of the initial wafer's dopant type


2. **Initial Oxide Growth**
在diffusion的處理，已經移除了wafer上的粒子、有機無機汙染物、原生氧化層
IOG有以下的功能：
- 保護表面不受汙染
- 避免在impantation時受到過多傷害
- 幫助控制dopants的深度
3. **1st Mask**
mask層決定了產物要被implanted來形成n-wells(為了pMOS transistors)的區域
4. **n-well Implant (High energy)**
曝光區域覆蓋特定區域從ion implantation保護wafer。Windows, or openings, in the photoresist allow high-energy positive dopant ions to penetrate into the upper surface of the epilayer(~1$\mu m$ junction depth)
5. **Anneal**
4 things occur：
1. 新的氧化層長在赤裸裸的silicon上
2. 更高的溫度使dopants的活動更大(diffusion)
3. implant造成的傷害被修復
4. 在dopant原子跟矽原子的鍵結被激活，讓dopant原子成為晶格結構的部分 (electrical activation)

### HW
1. Q9.1 : List the siz distinct production areas in a wafer fab and give a short description of each area
:::spoiler **Ans here**
* **Diffusion**: the area where high-temperature processing and film depositions are performed.
* **Photolithography**: light up by yellow fluorescent, photolithography is to photograph the image of a circuit pattern onto the photoresist that coats the wafer surface.
* **Etch**: creating a permanent pattern on the wafer in areas not protected by the photoresist pattern.
* **Ion Implant**: to strip off the photoresist and thoroughly clean the wafer.
* **Thin Films**: depositing dielectric and metal layers during different steps of the manufacturing process.
* **Polish**: to planarize the top surface of the wafer by lowering the high topography to be level with the lower surface areas of the wafer.
:::
2. Q9.4 : What is the purpose of photolithography?
:::spoiler **Ans here**
photograph the image of a circuit pattern onto the photoresist that coats the wafer surface.
:::
---
期中分隔線
---
---

## 第十章 Oxidation
### 重點
* 氧化層薄膜的應用 (表10.1)
* 乾式與濕式氧化
* 氧化成長模型
### 內容摘錄
#### Intro
* **Grown oxide layer**
- 外加
+ high-purity oxygen
- 環境
+ elevated-temperature
+ the diffusion area of the wafer fab
- 反應
+ react with the silicon substrate
* **Deposited mtd**
- 外加
+ external silicon source
+ $\ce{O2}$
- 環境
+ a chamber
- 反應
+ form a thin film on the wafer surface
##### 自己的小畫線
> Grown的方法在反應時會消耗原有silicon，而deposit就不會。
> 命名會取"grow"的原因: indicate that temperature is used to cause the oxide to grow out of the silicon semiconductor material, actually consuming silicon in the process.
#### 氧化層薄膜 oxide film
* T between 750°C to 1100°C
* also referred to as **thermal oxide** or **thermal silicon dioxide**
* Another term for silicon dioxide is *glass*.
* Silicon dioxide is a dielectric material and will not conduct electricity

#### Nature of Oxide Film
* silicon surface exposed to $\ce{O2}$
$\to$ amorphous silicon dioxide grows
* atomic structure of this $\ce{SiO2}$ film = 4 $\ce{O2}$ with 1 $\ce{Si}$ (*tetrahedron cell*)
* melting T of 1732°C grown **intrinsic(pure) glass**
- 性質
+ strong adhesion
+ exhibits excellent dielectric properties
+ Over time, the native oxide layer will thicken to an upper limit of about 40Å
- 問題
+ nonuniform
+ usually a contaminant
#### **氧化層薄膜的應用**
* 氧化層的重要性
- 易於形成
- excellent interface with the underlying silicon material
* Diff ways in which an oxide layer is used to fabricate a microchip are:
1. Device scratch protection and contaminant isolation
2. impurity-mask barrier during doping
3. Dielectric layer between metal conductor layers
#### Uniform oxide growth (乾式/濕式氧化)
##### Dry Oxidation
>The **time** and **quality** of this reaction varies and is affected by the purity of oxygen gas supplied to the silicon wafer surface and the reaction temperature

$$
\ce{Si}\text{(solid)}+\ce{O2}\text{(gas)}\to\ce{SiO2}\text{(solid)}
$$
* The reaction **rate is increased** with an **increase in temperature**
##### Wet Oxidation
> When water is introduced into the rxn
> the rate of theoxidation reaction is increased further

$$
\ce{Si}\text{(solid)}+\ce{2H2O}\text{(vapor)}\to\ce{SiO2}\text{(solid)}+\ce{2H2}\text{(gas)}
$$
* it produces a **silicon dioxide film** and **hydrogen gas**
因氫分子易被氧化層捕捉，使其相較dry oxygen來說較不緻密。
#### Oxidation Growth Model

### HW
1. Q10.1: What is the difference between a grown and deposited oxide layer
:::spoiler **Ans here**
A grown oxide layer occurs on a wafer by providing externally supplied high-purity oxygen in an elevated-temperature environment to react with the silicon fab.
A deposited oxide later is generated by using an external silicon source and O2 and reacting these materials in a chamber to form a thin film on the wafer surface.
:::
2. Q10.12: State the chemical reaction for dry oxidation. At what temperature range does this reaction usually take place?
:::spoiler **Ans here**
$$ \ce{Si}\text{(solid)}+\ce{O2}\text{(gas)}\to\ce{SiO2}\text{(solid)}
$$
* 750°C to 1100°C
:::
3. Q10.15: What is diffusion? How does this occur in thermal oxidation?
:::spoiler **Ans here**
Diffusion is the movement of one material through another. Atoms diffuse from regions of high concentration to regions of low concentration for solid, liquid or gas states.
Diffusion of oxygen atoms occurs during thermal oxidation.
:::

## 第十一、十二章 Deposition
### 重點
* 多層金屬化定義
* 薄膜所需特性
* 薄膜沉積
- CVD系統: APCVD、LPCVD、PECVD
- PVD - 蒸鍍、濺鍍
### 內容摘錄
#### 簡介早期的設計、裝配半導體
The design and fabrication of early semiconductor consist of :
1. fabricating the semiconductor devices in silicon
2. interconnecting the devices to one metal conducting layer sandwiched between silicon dioxide as the dielectric material
* This technology was an extension of the first **planar transistors** made in the SSI era
* The critical dimension was well over **one micron**
* wafer表面不平整

* 隨著科技進步，需要新的金屬導體來維持電性上的表現(electrical performance)
* 先進的介電材料在金屬薄膜間沉積，提供了更足夠的絕緣保護

#### Film Terminology
***Multilevel metallization***:
metal and dielectric layers needed to interconnect the densely packed devices on the wafer. (如果沒介電絕緣的保護會發生短路)
***vias***:
The metal layers are connected by openings in the dielectric film.

#### Metal & Dielectric Layers
##### Metal Layers
* ***Aluminum metalization*** is the use of **aluminum alloy** for interconnect wiring
* Al metal deposited on entire surface of the wafer in a solid thin film and then etched to define the width and spacing of the **interconnect lines**
* Each metal layer can be referred to as Metal-1, Metal-2, and so on.
* *Critical layers* are those meal layers with linewidths etched to the critical dimension of the device
* Crital layer are **sensitive to particulate contamination** (killer defects) and reliability issues such as **electromigration** are more pronounced in fine geometry linewidths

##### Dielectric Layers
* The dielectric layer between the active devices in silion and the first metal layer is termed the ***first interlayer dielectric (ILD-1)***
* The important function of the ILD-1 layer is to isolated transistor devices in two ways:
- Elecrically from the metal interconnect layers
- Physically from contamination sources such as mobile ions
* The *interlayer dielectric (ILD)* is used between **different metal layers in the device**
- Serves as an insulating film between two conducting metals or adjacent metal line
- It has traditionally been **silicon dioxide ($\ce{SiO2}$)** with a dielectric constant of around 3.9 to 4.0
* A *thin film* is a thin, solid layer of a meterial created on a substrate
- 如果一個固體材料有3D(長、寬、厚度)，**a thin solid film** 就有其中一維(通常是厚度)，而且比另外兩個小很多
- Thin-film 綁在wafer substrate上(通常比film厚許多)
- 因為離substrate很近，對薄膜材料會有物理、機械、化學、電性上的影響

#### Film Deposition
The Film Characteristics
* Good step coverage
* Ability to fill high aspect ratio gaps (conformality)
* Good thickness unifotmity
##### Film-Step Coverage
* It is desirable for thin films to maintain a uniform thickness over surface features
* If the film thins excessively at a step, this can cause high stress, electrical shorts, or undesirable induced charges in the device

##### High Aspect Ratio Gaps
* A small gep (trench or hole) is characterized by its *aspect ratio*, which is defined as the ration of its depth to width
* Aspect ratio is expressed as a ratio, such as 2:1, which in this case means the gap depth is two times the width
* Examples of gaps that require effective gap-fill capability are vias passing through the interlayer dielectric (ILD) and trenches for shallow trench isolation (STI)

##### Film Growth
* A deposited film grows in three distinct stages
- *nucleation*: where clusters of stable nuclei are formed
- *nuclei coalescence* into clusters, also referred to as *island growth* (These randomly oriented island clusters grow based on surface mobility and the density of the cluster)
- The island clusters continue to grow and eventually develop into the third stage, a *continuous film*

#### Stages of Film Growth
1. 成核：氣體分子聚集在一起形成穩定的核團
2. 聚集：小的團聚集成塊狀
3. 連續薄膜：塊狀聚集的越多就可以形成連續薄膜

#### Techniques of Film Deposition

##### Chemical Vapor Deposition
The Essential Aspect of CVD
1. **Chemical action** is involved, either through chemicalreaction or by thermal decomposition (referred to aspyrolysis).
2. All material for the thin film is supplied by an **external source**.
3. The reactants in a CVD process must start out in the **vapor phase** (as a gas).
:::danger
3個黑體關鍵字考試要寫到
:::
##### Schematic of CVD Transport and Reaction Steps

#### Types of CVD Reactors and Principal Characterictics

##### APCVD (Atmospheric Pressure CVD)
* the reactor must be designed to have optimum reactant gas flow to every wafer in the system. (必須設計成讓最佳反應氣體能通到系統內每片wafer)
* These equipment designs use a belt or conveyor to carry the wafer samples through the reactor gases, which flow through the center of the reactor.
* Continuous-processing APCVD systems have
- high equipment throughput, good uniformity
- the capability to process large-diameter wafers
* APCVD systems do have problems with
- high gas consumption
- often need frequent reactor cleaning
> Since film deposition also takes place on the conveyor as well as the wafer, the belt transport system must be cleaned (sometimes it is incleaned in situ, or during use)
- deposited films often exhibit poor step coverage


##### Low pressure CVD (LPCVD)
* LPCVD are ==more common== now than APCVD because of their
- lower cost
- higher production throughput
- superior film properties
* LPCVD operates at a ==medium vacuum== (about 0.1 to 5 torr), and employs temperatures between ==300 and 900°C==
* The LPCVD reactor design favors the hot-wall reactor type so that uniform temperature control is achievable over a large operating length
* Since LPCVD reactors are often hot wall, particles deposit on the reactor wall
* Hot-wall reactors require periodic reaction chamber cleanup of particlesby routine maintenance


##### Plasma-Assisted CVD
* relies on plasma energy, in addition to thermal energy, to initiate and sustain the chemical reactions necessary for CVD
* The advantages of using plasma during CVD are:
1. **Lower processing temperature** (250 - 450C)
2. Excellent gap-fill for high aspect ratio gaps (with high density plasma)
3. Good film adhesion to the wafer
4. High deposition rates
5. High film density due to low pinholes and voids

###### Film Formation
* The plasma-assisted CV reaction necessary to form a film occurs when RE power is used to break up gas molecules in a vacuum
* The wafer is usually heated in order to assist the surface reactions and reduce the level of undesirable contaminants, such as hydrogen.

###### Plasma-Enhanced CD (PECVD)
* The development of *plasma-enhanced* CVD (PECVD) uses plasma energy to create and sustain the CVD reaction.
* The important difference is the much lower PECVD deposition temperature.
> For instance, silicon nitride (Si,N,) is depositedusing LPCVD at 800 to 900°C, yet cannot be deposited over aluminum metallization because Almelts at 660°C. On the other hand, silicon nitride deposited with PECVD at a temperature of 350°Cis suitable for this application
* A PECVD reactor is typically a cold-wall plasma reactor, with the wafer heated in its chuck while the remaining parts of the reactor are unheated
* Deposition parameters must be controlled to ensure the temperature gradient does not affect the film thickness uniformity
* Cold-wall reactors create fewer particles and require less downtime for cleaning

###### Film Formation during Plasma-Based CVD

###### PECVD

##### Physical Vapor Deposition
* covers two major methods:
- *evaporation*
- *sputtering*
* **Evaporation is used primarily for metals**. The surface of a metal sample held in a crucible **is heated with an incident **electron beam**. The flux of vapor atoms from the crucible is allowed to reach the wafer.
* Such evaporation must be done under high-vacuum conditions.
* Evaporation with an e-beam is **quite directional**, allowing interesting **shadowing effects** to be used.


* Sputtering is a process in which chemically inert atoms, such as argon, are **ionized** in a glow discharge (also called a plasma)
* **The ions are accelerated into a target by the electric field** in the so-called *dark space* at the boundary of the plasma
* Atoms from the target are knocked out (the sputtering process), and these atoms are allowed to reach the substrate
* Sputtering takes place in a **low-pressure gas environment**
* It **is less directional than e-beam evaporation** and typically can **achieve much higher deposition rates**.


### HW
1. Q11.5: Define the aspect ratio. Why is a high-aspect ratio important for ULSI devices?
:::spoiler **Ans here**
The aspect ratio of a small gap is defined as the ratio of its depth to width. The aspect ratio is important because the ability to fill very small gaps and holes on the surface of the wafer has become one of the most important film characteristics for devices.
:::
2. Q11.6: List and describe three stages of film growth.
:::spoiler **Ans here**
1) Nucleation: clusters of stable nuclei are formed,
2) nuclei coalescence: also referred to as island growth where randomly oriented island clusters grow based on surface mobility, and
3) continuous film: where the island clusters meet and form a solid sheet that spreads across the substrate surface.
:::

## 第十三章 Photolithography: Surface Preparation to Soft Bake
### 重點
* 微影之基本觀念，包括製程、DC、光頻譜、解析度及曝光度。
* 正及負雕像術之差異。
* 微影8個基本步驟。
* 正及負光阻的物理性質。
* 傳統i-line光阻的化學性及應用。
* 深紫外光（DUV）光阻的化學性及優點。

### 內容摘錄
#### 基本觀念
* Photolithography produces a **three-dimensional pattern** on the surface of the wafer using a light-sensitive photoresist material and **controlled exposure to light**.
* photolithography別稱：**photo, lithography, masking, and patterning**.

#### Photolithography Concepts
* Patterning Process
- Photomask
- Reticle
* Critical Dimension Generations
* Light Spectrum
* Resolution

#### *reticle* 和 *mask* 間的區別
##### *reticle*
1. 搭配固定機(stepper)
2. 有reduction less (當UV光穿過的時候會將光做倍率縮放，投影在wafer上面積會比在reticle上面積小
3. 有1顆die或4顆die的設計(layout)
4. 4:1的比例：若reticle上面線寬4mm那wafer上只剩1mm

##### *mask*
1. 搭配接觸/進階式曝光機(Contact/Proximity Aligner System)
2. mask多大wafer上曝光的面積就有多大
3. 1:1的比例
:::danger
可能考：請說明兩者間的差別還有在Photolithography上面使用的時候各自優缺點。
:::

#### Light Spectrum
Light Spectrum Energy is required to activate the photoresist and transfer the pattern from thereticle. The source of energy is in the form of radiation, typically an **ultraviolet (UV) light** source.

#### Resolution
Resolution is the ability to differentiate between **two closely spaced features on thewafer surface.** (能辨別兩個很靠近的feature size
:::danger
曾經考過 Resolution
:::

#### Important Wavelengths for Photolithography Exposure

#### Photolithography Processes
* Negative Resist
- Wafer image is **opposite of mask image**
- Exposed resist hardens and is insoluble
- Developer removes unexposed resist

* Positive Resist
- Mask image is **same as wafer image**
- Exposed resist softens and is soluble
- Developer removes exposed resist

#### Eight Steps of Photolithography
:::danger
期末考很常出現：問答、給圖說明步驟
:::

##### Step 1: Vapor Prime
The first step in photolithography is to clean, dehydrate, and prime the surface of the wafer. The purpose of these steps is to **promote good adhesion between the photoresist and the wafer surface.**
Immediately after the dehydration bake, the wafer is primed with hexamethyldisilazane (HMDS), which acts as an **adhesion promoter.**
用氣體的方式蒸塗在wafer表面，先上HMDS(很毒要小心)它光阻和substrate的附著力較好。

##### Step 2: Spin Coat
the wafer is coated with the liquid photoresist material by a spin coating method.
The wafer is mounted on a vacuum chuck, which is a flat metal or teflon disc that has small vacuumholes on its surface to hold the wafer.
then the water is spun to obtain a uniform coating of resist on the wafer.
其實也不是完全liquid而是稠狀液體，會用旋轉塗布機去旋塗在wafer表面。
會有一些設定好的參數，如轉速、

==Process Summary:==
* Wafer is held onto vacuum chuck
* Dispense ~ 5ml of photoresist
* Slow spin ~ 500 rpm
* Ramp up to ~ 3000 to 5000 rpm
* Quality measures:
- time
- speed
- thickness
- uniformity
- particles and defects

##### Step 3: Soft Bake
this bake is to drive off **most of the solvent** in the resist. The soft bake process improves **adhesion**, promotes resist uniformity on the wafer, and yields better linewidth control during etching. Typical soft bake temperatures are **90 to 100°C for 30 seconds** on a hot plate,

==Characteristics of Soft Bake:==
* **Improves Photoresist-to-Wafer Adhesion**
* Promotes Resist Uniformity on Wafer
* Improves Linewidth Control During Etch
* **Drives Off Most of Solvent in Photoresist**
* Typical Bake Temperatures are 90 to 100°C
- For About 30 Seconds
- On a Hot Plate
- Followed by Cooling Step on Cold Plate

##### Step 4: Alignment and Exposure(對準和曝光)
the mask and wafer are exposed to controlled UV light to transfer the mask image to the resist-coated wafer
* 轉移圖案到wafer上
* 用UV light曝光


==Process Summary:==
* Transfers the mask image to the resist-coated wafer
* Activates photo-sensitive components of photoresist
* Quality measures:
- linewidth resolution
- overlay accuracy
- particles and defects

##### Step 5: Post-Exposure Bake (PEB)
* 如果是用deep UV作為光源一定要做曝後考才能完成曝光顯影動作，其他在傳統上可做可不做
* 現在漸漸變成所有都要做
--
* Required for Deep UV Resists
* Typical Temperatures 100 to 110°C on a hot plate
* Immediately after Exposure
* Has Become a Virtual Standard for DUV and Standard Resists

##### Step 6: Develop
The soluble areas of the photoresist are dissolved by liquid developer chemicals, leaving visible patterns of islands and windows on the wafer surface.
==Process Summary:==
* Soluble areas of photoresist are dissolved by developer chemical
* Visible patterns appear on wafer
- windows
- islands
* Quality measures:
- line resolution
- uniformity
- particles and defects

##### Step 7: Hard Bake
A post-development thermal bake, referred to as hard bake, is required to evaporate the remaining photoresist solvent and improve the adhesion of the resist to the wafer surface.

* A Post-Development Thermal Bake
* **Evaporate Remaining Solvent**
* Improve Resist-to-Wafer Adhesion
* Higher Temperature (120 to 140°C) than Soft Bake

#### Develop Inspect
* Inspect to Verify a Quality Pattern
- Identify Quality Problems (Defects)
- Characterize the Performance of the Photolithography Process
- Prevents Passing Defects to Other Areas
+ Etch
+ Implant
- Rework Misprocessed or Defective
Resist-coated Wafers
* Typically an Automated Operation

#### Photoresist
* Photoresist
- Types of Photoresist
- Negative Versus Positive Photoresists
* Photoresist Physical Properties
* Conventional I-Line Photoresists
- Negative I-Line Photoresists
- Positive I-Line Photoresists
* Deep UV (DUV) Photoresists

##### Types of Photoresist
* 負光阻：照到UV光的地方交鏈鍵結會接起來&固化，且不容易溶解在顯影液
* 正光阻：照到UV光的地方會破壞交鏈鍵結
* 負光阻用比較少的原因：沖顯影液時會吸收，然後會讓圖案失真

##### Photoresist Physical Properties
* Resolution:
可以辨別做光阻的pattern最小feature size
* Contrast
* Sensitivity(PS: 不要跟第一個搞混)
指單位面積所要提供光阻曝光所需的最小能量(焦耳
> *exposure dose*(曝光劑量):
> 全部(整片)的面積曝光所需的劑量總量
* Adhesion
how strongly the resist sticks to the substrate.
* Etch resistance
- The resist film must maintain its adhesion and protect the substrate surface from the subsequent wet and dry etch processes.
- This property is known as *etch resistance*.
* Surface tension
Resist has molecular forces that create a relatively high surface tension so that the resist molecules hold together during the various process steps.
At the same time, the surface tension of resist must be low enough to provide for good flow and wafer coverage during application.

##### Negative Resist Cross-Linking

##### PAC as Dissolution Inhibitor in Positive I-Line Resist

##### Deep UV (DUV) Photoresists
* **i-line** wavelength of **365 nm** --- a CD of **0.35 $\mu m$** was achievable.
* **reduce the wavelength of** the exposure light source to a value of around 250 nm (0.25 p.m) --- a CD of 0.25 um on critical layers
* **248 nm** UV wavelength referred to as **deep UV (DUV)**

##### Chemical Amplification for DUV Resists:

##### Chemically Amplified (CA) DUV Resist

### HW
1. Q13.1: What is photolithograohy?
:::spoiler **Ans here**
Photolithography produces a three-dimensional pattern on the surface of the wafer using a light-sensitive photoresist material and controlled exposure to light.
微影是利用光敏的光阻材料及控制其曝光量以在晶圓上產生三維的圖案
:::
2. Q13.5: What is overlay accuracy, and how does this contribute to the mask overlay budget?
:::spoiler **Ans here**
Overlay accuracy is the precise alignment between the pattern on the mask and the existing features on the wafer surface.
Since multiple masks are used during patterning, any overlay misalignment contributes to the total placement tolerances between the different features on the wafer surface, or mask overlay budget.
重疊精確：微影須將光罩圖案和已存在晶圓表面尺寸做精確對準
重疊預算：若重疊未對準使晶圓上不同尺寸間有位置扭曲，此為重疊預算，重疊預算高則會大幅降低電路密度，限制元件尺寸大小和IC特性
:::
3. Q13.7: Explain the difference between negative and positive lithography.
:::spoiler **Ans here**
Negative lithography prints a pattern on the wafer surface that is opposite the pattern in the mask. Positive lithography prints a pattern on the wafer that is the same pattern as on the mask.
負光阻：光阻曝光後其晶圓表面上的圖案和光罩上是相反的，光阻變成不溶解且鍵結硬化
:::

## 第十四章 Photolithography: Alignment and Exposure
### 重點
1. 微影中對準及曝光之目的。
2. 曝光光源主要有哪兩種?其激發頻譜有何不同?對CD的影響?
3. 曝光設備，各世代機台的優缺點。
4. 標線板在微雕像中之用途?
5. 對準技術。

### 內容摘錄
* **step-and-repeat**
1. The water is aligned to the reticle so that the pattern can be transferred to the proper location on the wafer surface.
2. Once the best focus and alignment are obtained, a shutter opens to allow UV light to pass from the illuminator to the reticle through a projection lens and then onto the resist-coated wafer.
3. Once a pattern is exposed, the stepper will step to the next location on the water and repeat the alignment and exposure.

#### Reticle Pattern Transfer to Resist

#### Layout and Dimensions of Reticle Patterns
* 小十字用來做對準，也叫align mark
* 不同層對應不同光照來處理，表上列出每一道光照的圖層

##### Optical Exposure
* 線寬越小，對曝光光源要求越嚴苛，波長越短

##### Electromagnetic Spectrum
* 所有可見與不可見的電磁波統稱為電磁頻譜(Electromagnetic Spectrum)
* UV spectrum (4nm~450nm)有以下幾種：
1. The vacuum ultraviolet (VUV)：157nm
2. DUV：248nm、193nm
3. Extreme UV (EUV)：13.5nm
* 必須在黃光下作業

#### Ultraviolet Spectrum

#### Optical Lithography
Exposure Sources：
1. **Mercury Arc Lamp**
- The high-pressure *mercury arc lamp* is used as the UV illumination source in all conventional i-line steppers
- the useful UV wavelength emissions for a mercury arc lamp between about 240 nm and 500nm in length
2. **Excimer Laser**
- **light intensity(光強度)：I=power/area 每單位面積功率**
- **Expose dose(曝光劑量)=I*t 光強度$\times$曝光時間**
- **Energy=p*t*area 曝光所需能量**

* i-line 的光阻劑量大概 100mJ/cm$^2$
* 在DUV波段要花費太多時間不符成本
##### Excimer Laser (準分子雷射)
* 主要的好處在於能提供DUV更多的光強彌補mercury arc lamp效率不好的問題
* laser light source: An exotic molecule fromed an atom of a noble gas and halogen (鈍氣分子&鹵素，如ArF)


#### Photolithograhy Equipment
* Contact Aligner
- 每一次曝光就曝整片wafer
- 光照和光阻是接觸的(曝光的時候光照放在光阻上)。
優點：好的解析度
缺點：會帶來一些汙染、壽命很短
* Proximity Aligner
- 每一次曝光就曝整片wafer
- 光照和光阻沒直接接觸，有縫隙
- UV光前進時會有繞射問題，所以解析度會有一些失真
* Step-and-Repeat Aligner (stepper)
- 一次只能曝1~4顆
- 倍率：4X、5X、10X
- 由於是大到小的比例縮放，更容易fabricate the reticle
* Extreme Ultraviolet (EUV) Lithography
* System (not included in the exam

#### Reticles Materials
* 材料用熔融矽土，好處是很低的熱膨脹係數，即便溫差很大線寬也不會影響
* 光穿透率要好、沒有缺陷
* 上面會鍍鉻膜，因為鉻膜可阻擋UV光前進

#### Comparison of Reticle Versus Mask

### HW
1. Q14.5: Describe the relationship between light exposure wavelength and image resolution.
:::spoiler **Ans here**
曝光波長越短，特徵尺寸解析越小
曝光波長越短，解析力愈高(能解析的尺寸R越小)
:::

## 第十五章 Photolithography: Resist Development and Advanced Lithography

### 重點
1. 傳統與化學倍增式DUV光阻為何與如何執行曝光後烘烤。
2. 分別針對傳統與化學倍增式DUV光阻，描述其負與正光阻顯影製程。
3. 說明為何光阻顯影後，需進行硬烤處理。
4. 解釋顯影後檢查所具有之優點。

### 內容摘錄
#### POST-EXPOSURE BAKE
* 使用化學倍增式光阻一定要做曝後烤
* 做的好處：可以改善光阻的adhesion、減少駐波效應

#### DUV Post-Exposure Bake (PEB)
* 化學倍增式光阻有PAG，做曝後烤可加速酸化反應讓它易溶於顯影液

##### Chemically Amplified (CA) DUV Resist

#### Conventional I-Line PEB
* 對於I-Line的光阻來說曝後烤可做可不做
* 用抗反射層，也能減緩當UV光打過去有一部份反射造成線寬波浪形
* Reduction of Standing Wave Effect due to PEB

### Develop
* Negative Resist
* Positive Resist

#### Develop
The three primary types of development problems are
1. **underdevelopment**
appears wider than a normal line and will have sloping sidewalls.
2. **incomplete development**:
has residual resist on the substrate that should have been removed during develop.
3. **overdevelopment**
removes too much resist causing features to appear narrower and poorly-defined.


#### Negative Resist
* 2$\mu m$以下尺寸的光阻不適用，因為會吸顯影液，造成swelling & distortion

#### Positive Resist
* the most common resists used in submicron wafer fabrication due to improved linewidth resolution.
* he two general types of positive resists used in wafer microlithography are
- conventional DNQ i-line resists
- chemically amplified (CA) DUV resists
* Although these two resists are very different chemically, it is generally truethat phenolic resin is soluble in a base solution.

### Developer
have selectivity(選擇比)
* 對兩種反應的差異很大
* 需要反應的A會反應的很快，相對B就不靈敏
* 如果顯影選擇比很高，顯影效果會比較好

### HARD BAKE
* 可以把光阻裡剩餘的solvent去除
* 讓光阻變堅硬 (在之後蝕刻或離子植入時起到保護作用
* 改善光阻和substrate的附著力

### DEVELOP INSPECT
在進行蝕刻或離子植入前要經過顯影後檢視看顯影的圖跟設計是否一致
因為到了後面就沒法重做

### HW
1. Q15.3: Why is temperature uniformity important for PEB?
:::spoiler **Ans here**
PEB temperature non-uniformity (both in steady-state and transient phases) impacts across-wafer CD uniformity
:::
2. Q15.17: Explain why hard bake is done.
:::spoiler **Ans here**
* 可以把光阻裡剩餘的solvent去除
* 讓光阻變堅硬 (在之後蝕刻或離子植入時起到保護作用
* 改善光阻和substrate的附著力
:::

## 第十六章 Photolithography: Etch

### 重點
1. 重要的蝕刻參數。
2. 何謂乾蝕刻，優點?
3. 物理性與化學性蝕刻機制。

### 內容摘錄
#### Intro
* 可以以物理/化學性方式去除掉晶圓表面不要的材料
* 蝕刻選擇比要高

#### Etch Process
Two basic types of etch processes are used in semiconductor manufacturing:
* dry etch
- 使用氣體電漿進行蝕刻
- 以物理(轟擊)的方式去除
- 開機費貴貴
* wet etch
- 使用丙酮進行蝕刻
- 常用強酸去除(例如BOE(緩衝氧化物刻蝕液)，是由氫氟酸、醋酸、磷酸所組合
- 只能用在大面積尺度，線寬太小蝕刻液會吃不進去

#### Etch Parameters
##### Etch rate
* 蝕刻速率=所移除材料的總量(通常以薄膜厚度)/蝕刻時間
* 蝕刻速率與蝕刻液濃度成正比
* **loading effects**
在大面積蝕刻蝕時，跟蝕刻液反應會吸收掉蝕刻液的濃度
最後蝕刻的效率會較慢
反之在小面積比較不易稀釋蝕刻液，速率較快

##### Etch profile
*Etch profile*: refers to the shape of the sidewall of the etched feature
分成兩種：
* **isotropic(等向性)**：
- 定義：所有方向蝕刻速率都一樣
- 導致 **undercutting(底切現象)**，線寬失真
- 常發生在濕蝕刻，不適合去做精確的線寬
* **anisotropic(異向性/非等向性)**
- 定義：只在一個方向蝕刻(通常是往下侵蝕)
- 能精確控制線寬
* 乾/濕蝕刻造成的側壁輪廓

##### Etch bias
* 定義：a measure of the change in linewidth or space of a critical dimension (CD) after performing an etch process
* 通常由底切所造成抑或是蝕刻輪廓
* 公式：$\text{Etch bias}=W_b-W_a$
> 其中，
> $W_b=$ 蝕刻前光阻原來的線寬
> $W_a=$ 蝕刻完光阻移除後最終的線寬
:::danger
這邊講了非常多蝕刻的名詞，
像profile、etch bias都有可能會出現在解釋名詞，所以定義要搞清楚
:::
* overetch

##### Selectivity
* 定義：how much faster one film etches than another film under the same etch conditions
* 公式：$\displaystyle S_R=\frac{E_f}{E_r}$
> 其中，
> $E_f=$ 進行蝕刻時薄膜的蝕刻速率
> $E_r=$ masking layer的蝕刻速率(e.g 光阻)
* 好的選擇比比例至少100:1以上(想要的比不想要的侵蝕快100倍以上)

##### Uniformity
* 定義：a measure of the capability of the process to etch evenly across the entire surface area of the wafer, across the entire wafer lot, and from lot to lot

#### Dry Etch
##### Advantages of Dry Etch over Wet Etch
1. Etch profile is anisotropic with excellent control of sidewall profiles
乾蝕刻可以選擇氣體來源使薄膜可以形成異向性的蝕刻，對於側壁輪廓的控制就能精確
2. Good CD control
線寬(CD)控制也非常的好
3. Minimal resist lifting or adhesion problems
使光阻不容易掀掉和解決附著力的問題
4. Good etch uniformity within wafer, wafer-to-wafer and lot-to-lot
5. Lower chemical costs for usage and disposal
因為濕蝕刻都是用強酸/鹼下去做薄膜侵蝕，必須經過一定程序處理掉
:::danger
這五點曾經出現在期末考問答題
:::

##### Chemical and Physical Dry Etch Mechanisms

### HW
1. Q16.1: Define etch. What is the goal of etching?
:::spoiler **Ans here**
Etch is the process of selectively removing unneeded material from the wafer surface by using either chemical or physical means. The goal of etching is to accurately reproduce the mask features on the wafer.
:::
2. Q16.2: What are the two types of etch process? Give a short description of each type.
:::spoiler **Ans here**
Dry etch and wet etch. Dry etch exposes the wafer surface to a plasma created in the gaseous state. The plasma passes through the mask openings and interacts physically or chemically (or both) with the wafer to remove the surface material. Wet etch uses liquid chemicals such as acids, bases and solvents to chemically remove the wafer surface. It is generally applicable to geometries greater than $3\mu m$.
:::

## 第十七章 Doping Processes

### 重點
1. 解釋晶圓製作中，摻雜的目的與應用。
2. 討論摻質擴散的原理與製程。
3. 提供有關離子植入之概要說明，包括它的優缺點。
4. 討論題子植入時，有關劑量與範圍的重要性。
5. 解釋何謂離子植入之退火及通道效應。

### 內容摘錄
#### intro
* 定義：the introduction of a dopant into the crystal structure of a semiconductor material to modify its electronic properties (e.g., electrical resistivity)
* Dopant species are also referred to as impurities(這是需要雜質的，像是加進去的dopants) but should not be confused with contaminating impurities (不要的稱為汙染物)
* 有兩種技術可將dopant的元素加進wafer中：
- **thermal diffusion**
Thermal diffusion uses high temperature to move the dopant through the silicon lattice structure
+ This method is dependent on ==time and temperature==
- **ion implantation**
Ion implantation introduces dopants into the substrate through a ==high-voltage ion bombardment==
+ The dopants are implanted into the wafer through ==high-energy collisions at the atomic level==

##### 常用dopants

#### Doped Regions
* 擴散的時候會拿一些元素當作擋罩(圖上是用oxide)
- 裸露出來的就是要doping的地方
* doping的區域稱作 **dopant profile**
* 在離子植入方面，擋罩通常是光阻
- 因為溫度低光阻不會被熔融所以能用的擋罩比較多元(相對diffusion在高溫下進行，所以通常只能用oxide/nitride當擋罩

#### Diffusion
* 物質由高往低濃度移動
* 氣、液、固態都可以發生
* 當高濃度dopant打進wafer會產生固態的擴散
* 不同dopant有著不同的 **diffusivity(擴散係數)**
- D越大速度越快
- 擴散係數隨溫度增加
* 在wafer上dopant有兩種移動的模式：
- **interstitional(間隙式替換)**
用填入空隙的方式進去
主要進行這模式的元素：Au、Cu、Ni
- **substitutional(替代式替換)**
用替換的方式進去
主要進行這模式的元素：As、P

##### Solid Solubility()
定義：==At a given temperature==, there is a limit to how much dopant can be absorbed by the silicon. This is referred to as the **solid solubility limit**
* Each a particular dopant has a solid solubility limit

#### Ion implantation
定義：a method for introducing controlled amounts of dopants into the silicon substrate to change its electronic properties.
* 物理反應，
* 沒有極限的問題打多少都沒關係
* 大大大優點：可以精確的控制打進去dopant的濃度和深度

##### 控制dopant濃度/深度

##### Overview
Ion implant processing is done in one of the most complex semiconductor processing tools, called the *ion implanter*
1. The implanter has an ion source component that creates ==positive-charged== dopant ions from a source material.
2. The ions are extracted and then separated in a mass analyzer to form a beam of the desired dopant ions.
* The number of ions in the beam is related to the ==concentration of dopants== introduced into the wafer
3. The beam of ions is accelerated in a voltage field to attain a high velocity (on the order of 10 cm/sec)
* Because of the high velocity, the ions have kinetic energy that is used to implant the dopants into the silicon crystal lattice structure of the target wafer
4. The beam scans the wafer to provide uniform doping across the wafer surface
5. Implantation is followed by a ==thermal anneal step to activate the dopant ions== in the crystal structure
* All implanter processing is done in a high vacuum

##### Advantages of Ion Implantation(會考很重要無限星星)
1. **Precise control of dopant concentration**
3. **Good dopant uniformity**
4. **Good control of dopant penetration depth**
5. **Produces a pure beam of ions**
6. **Low temperature processing**
7. **Ability to implant dopants through films**
8. **No solid solubility limit**

##### Disadvantages of Ion Implant
* 高能量離子束會把原本矽原子位置給打亂，需回復鍵結
* 有兩種能量喪失的形式：
- **Electronic stopping**
Electronic stopping of dopant atoms is caused by interactions with the target electrons, similar to stopping a projectile in a thick medium, such as a child jumping into a pile of plastic balls
- **Nuclear stopping**
Nuclear stopping of implanted ions is caused by collisions between atoms that cause a displacement of silicon atoms.
+ It can be visualized as the collision between two hard spheres, such as billiard balls.
+ Depending on the ion mass and energy, an implanted atom can displace as many as 104 silicon atoms by nuclear collisions before coming to rest
* 停在多少深度取決於喪失多少能量

#### Annealing
* Ion implantation damages the silicon lattice by knocking atoms out of the lattice structure.
* These interstitial dopants are electrically inactive until activated by a high-temperature annealing step.
- 通常都是在相對高溫+維持一段時間，讓他有足夠的溫度和能量去完成活化的反應，修補這些鍵結
- Electrical activation of dopants occurs as a function of time and temperature, with longer times and higher temperatures increasing the dopant activation
- There are two basic methods for heating the implanted wafer for anneal:
+ Furnace anneal
+ Rapid thermal anneal (RTA)

#### Channeing
There are four ways that channeling is controlled during implant:
1. wafer tilt,
2. screen oxide layer
3. ~~preamorphization of the silieen~~
4. ~~usingdopants with greater amu's (atomie mass units)~~

##### Wafer Tilt
直接把wafer轉下（7度）就比較不會有某一個方向通通不會有能量損失的問題

##### Screen Oxide Layer
用一層很薄的oxide layer當作screen oxide layer當犧牲層，讓ion beam有能量的損失使其停在較淺介面，做完植入再去除掉犧牲層

### HW
1. Q17.1: What is doping?
:::spoiler **Ans here**
Doping is the introduction of a dopant (also known as an impurity) into the crystal structure of a semiconductor material to control its electronic properties (e.g., electrical resistivity)
:::
2. Q17.3: Give a short description of thermal diffusion.
:::spoiler **Ans here**
Thermal diffusion uses high temperature to move the dopant through the silicon lattice structure. This method is dependent on time and temperature
:::
3. Q17.4: Give a short description of ion implantation.
:::spoiler **Ans here**
Ion implantation introduces dopants into the substrate through a high-voltage ion bombardment. The dopants are implanted into the wafer through high-energy collisions at the atomic level
:::

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