---
# System prepended metadata

title: '** LAB 9 **'

---

# Lab 9
Name: Guru Rohith.G
Roll No.: CS22B022

---
## Question 1

**Code** (if required)
```verilog=
module ALU(
    input [1:0] operand1, 
    input [1:0] operand2, 
    input [1:0] control,  
    output reg [1:0] result 
);

    always @(*) begin
       
        case(control)
            2'b00: result = operand1 + operand2; 
            2'b01: result = operand1 - operand2; 
            2'b10: result = operand1 & operand2; 
            2'b11: result = operand1 | operand2; 
            default: result = 2'b00; 
        endcase
    end

endmodule

module MUX4to1(
    input [3:0] data, // 4-bit input data
    input [1:0] select, // 2-bit select signal
    output reg out // Output
);

    always @(*) begin
        
        case(select)
            2'b00: out = data[0];
            2'b01: out = data[1];
            2'b10: out = data[2];
            2'b11: out = data[3];
            default: out = 1'b0; 
        endcase
    end

endmodule

module ALU_with_MUX(
    input [1:0] operand1,
    input [1:0] operand2, 
    input [1:0] control, 
    output reg [1:0] result 
);

    wire [1:0] alu_output;
    ALU ALU_inst(.operand1(operand1), .operand2(operand2), .control(control), .result(alu_output));

    wire [3:0] mux_input;
    assign mux_input = {alu_output, 2'b00};

    wire [1:0] select_lines;
    assign select_lines = control;

    MUX4to1 MUX_inst(.data(mux_input), .select(select_lines), .out(result));

endmodule

```


---

## Question 2
**Code** 
```verilog=
module SimpleProcessor(
    input [7:0] instruction,
    input [7:0] data_in,     
    output reg [7:0] data_out 
);

    reg [7:0] memory [0:255]; 
    reg [7:0] R[1:2];         /
    
    // Instruction decoding
    reg [7:0] opcode;
    reg [7:0] dest_reg;
    reg [2:0] offset;
    reg [1:0] src_reg;
    
    // Extracting fields from instruction
    always @(*) begin
        opcode = instruction[7:6];
        dest_reg = instruction[5:4];
        offset = instruction[3:1];
        src_reg = instruction[0];
    end
    
    // Load operation
    always @(posedge src_reg) begin
        // Load instruction
        if (opcode == 2'b00) begin 
            data_out <= memory[R[src_reg] + offset];
        end
    end
    
    // Store operation
    always @(posedge src_reg) begin
        // Store instruction
        if (opcode == 2'b01) begin
            memory[R[src_reg] + offset] <= data_in;
        end
    end

endmodule

```


---

## Question 3
**CODE**
```cpp=
#include<stdio.h>

	int fib(int n){
	if(n>=3) {
		return (fib(n-1)+fib(n-2));
	}
	else if(n==1||n==2) {
		return 1;
	}
}
int main() {
	int a = 7;
	for(int i=1;i<=a;i++) {
		printf("%d\n",fib(i));
	}
	return 0;
}
```

![Screenshot 2024-04-08 223349](https://hackmd.io/_uploads/HyjtmjblA.png)

