---
# System prepended metadata

title: Lab 8

---


# Lab 8
Name: Guru Rohith.G
Roll No: CS22B022

---
## Question 1

### Verilog Code
```verilog=
module fwithh(sum,cout,a,b,c);
input a,b,c;
output sum,cout;
wire w1,w2,s;
halfadder h1(w1,w2,a,b);
halfadder h2(sum,s,w1,c);
assign cout = (w2|s);
endmodule

```
#### Test bench
```verilog=
module fullwithhalftb();
reg a1,b1,c1;
wire sum1,cout1;

    fwithh out(.sum(sum1),.cout(cout1),.a(a1),.b(b1),.c(c1));

initial 
begin
a1 = 0; b1 = 0; c1 = 0;
#100
a1 = 0; b1 = 0; c1 = 1;
#100
a1 = 0; b1 = 1; c1 = 0;
#100
a1 = 0; b1 = 1; c1 = 1;
#100
a1 = 1; b1 = 0; c1 = 0;
#100
a1 = 1; b1 = 0; c1 = 1;
#100
a1 = 1; b1 = 1; c1 = 0;
#100
a1 = 1; b1 = 1; c1 = 1;


end
endmodule
```
![Screenshot 2024-04-07 110125](https://hackmd.io/_uploads/HkAZxnJx0.png)

---
## Question 2

### Verilog Code
```verilog=
module rca4bitadder(
    input [3:0]a,b,
    input cin,
    output [3:0]sum,
    output c4);

wire c1,c2,c3;      

fulladder fa0(a[0],b[0],cin,sum[0],c1);
fulladder fa1(a[1],b[1],c1,sum[1],c2);
fulladder fa2(a[2],b[2],c2,sum[2],c3);
fulladder fa3(a[3],b[3],c3,sum[3],c4);
                
endmodule
####
module fulladder (
    input a,b,cin,
    output sum,carry
);

assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin)  | (cin & a) ;

endmodule
```
##### Testbench
```verilog=
module rca4bittb;
    reg [3:0] a, b;
    reg cin;
    wire [3:0] sum;
    wire c4;

    rca4bitadder uut(a, b, cin, sum, c4);

    
    initial begin
        
        cin = 0;
        a = 4'b0110;
        b = 4'b1000;
        #10; 
        a = 4'b1010;
        b = 4'b1010;
        #10; 
        a = 4'b0111;
        b = 4'b1111;
        #10; 
        a = 4'b1011;
        b = 4'b1001;
        #10;  
    end
endmodule
```
![Screenshot 2024-04-07 113717](https://hackmd.io/_uploads/H1lu_3kgR.png)


---

# QUESTION 3
### Code
```verilog=
module m21(Y, D0, D1, S);
output Y;
input D0, D1, S;
wire T1, T2, T3;
and_gate u1(T1, D1, S);
not_gate u2(T2, S);
and_gate u3(T3, D0, T2);
or_gate u4(Y, T1, T3);
endmodule
```
#### Testbench
```verilog=
`timescale 1ns/1ns

module tb_muxtb;

// Define inputs
reg D0, D1, S;

// Define output
wire Y;
m21 uut (
    .Y(Y),
    .D0(D0),
    .D1(D1),
    .S(S)
);
initial begin
    // Test vector 1
    D0 = 1'b0;
    D1 = 1'b0;
    S = 1'b0;
    #5; 
    
    // Test vector 2
    D0 = 1'b0;
    D1 = 1'b0;
    S = 1'b1;
    #5; 
    
    // Test vector 3
    D0 = 1'b0;
    D1 = 1'b1;
    S = 1'b0;
    #5; 
    
    // Test vector 4
    D0 = 1'b0;
    D1 = 1'b1;
    S = 1'b1;
    #5; 
    
    // Test vector 5
    D0 = 1'b1;
    D1 = 1'b0;
    S = 1'b0;
    #5;
    
    // Test vector 6
    D0 = 1'b1;
    D1 = 1'b0;
    S = 1'b1;
    #5; 
    
    // Test vector 7
    D0 = 1'b1;
    D1 = 1'b1;
    S = 1'b0;
    #5; 
    
    // Test vector 8
    D0 = 1'b1;
    D1 = 1'b1;
    S = 1'b1;
    #5; 
end
endmodule
```
![Screenshot 2024-04-07 181505](https://hackmd.io/_uploads/rytpSGge0.png)
