---
# System prepended metadata

title: LAB 8 CS22B014

---

**LAB 8**

Name : PRANAV CHALAVADI
Roll no.: CS22B014

**Question 1**
```verilog=


module fulladder(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
wire t1,t2,k;
halfadder(t1,k,a,b);
halfadder(s,t2,t1,cin)
or(cout,k,t2);
endmodule

module halfadder(s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

**Test bench**
module fulladder_test;
// inputs
reg a;
reg b;
reg cin;
// outputs
wire s;
wire cout;
    fulladder uut(.s(s),.cout(cout),.a(a),.b(b),.cin(cin));
initial begin
a=1'b0;b=1'b0;cin=1'b0;  
#2 a=1'b0;b=1'b0;cin=1'b1;
#2 a=1'b0;b=1'b1;cin=1'b0;
#2 a=1'b0;b=1'b1;cin=1'b1;
#2 a=1'b1;b=1'b0;cin=1'b0;
#2 a=1'b1;b=1'b0;cin=1'b1;
#2 a=1'b1;b=1'b1;cin=1'b0;
#2 a=1'b1;b=1'b1;cin=1'b1;    
end 
endmodule
```

![WhatsApp Image 2024-04-07 at 22.28.46](https://hackmd.io/_uploads/ry0OMLgg0.jpg)

**Question 2**

```verilog=

module rca(s,c,a,b,cin);
input [3:0]a,b;
input cin;
output [3:0]s;    
output c;
wire co,c1,c2;
    
fa g1(s[0],c0,a[0],b[0],cin);
fa g2(s[1],c1,a[1],b[1],c0);
fa g3(s[2],c2,a[2],b[2],c1);
fa g4(s[3],c,a[3],b[3],c2);
endmodule 

module fa(s,c,a,b,cin);
input a,b,cin;
output s,c;
wire s1,c1,c2;
ha h1(s1,c1,a,b);
ha h2(s,c2,s1,cin);
or(c,c2,c1);
endmodule
        
module ha(s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule    

**Test bench**
module rca_testbench;
// Input signals
  reg [3:0] a, b;
  reg cin;
  // Output signals
  wire [3:0] s;
  wire c;
  rca dut (s, c, a, b, cin);
  initial begin
    // Test cases with various input combinations:
    a <= 4'b0000; b <= 4'b0000; cin <= 0;  // All zeros
    #10;

    a <= 4'b0001; b <= 4'b0001; cin <= 0;  // Adding 1 and 1
    #10;

    a <= 4'b1111; b <= 4'b0001; cin <= 0;  // Adding largest and smallest values
    #10;

    a <= 4'b1001; b <= 4'b0110; cin <= 1;  // Adding with carry-in
    #10;

    a <= 4'b1111; b <= 4'b1111; cin <= 1;  
    #10;
end
endmodule
```

![WhatsApp Image 2024-04-07 at 22.28.46 (2)](https://hackmd.io/_uploads/rktkHLleC.jpg)

**Question 3**

```verilog=

module mux_2_1(a,b,s0,y);
output y;
input a,b,s0;
wire w1,w2,w3;
not(w1,s0);
and(w2,w1,a);
and(w3,s0,b);
or(y,w2,w3);
    // y = S̅0 * a + S0 * b
endmodule

**Test bench**
module mux_testbench;
//inputs
 reg a;
 reg b;
 reg s0;
//output
 wire y;
    mux_2_1 uut(.a(a),.b(b),.s0(s0),.y(y)) ;
    initial begin
a=1'b0;b=1'b0;s0=1'b0;  
#2 a=1'b0;b=1'b0;s0=1'b1;    
#2 a=1'b0;b=1'b1;s0=1'b0;  
#2 a=1'b0;b=1'b1;s0=1'b1;    
#2 a=1'b1;b=1'b0;s0=1'b0;  
#2 a=1'b1;b=1'b0;s0=1'b1;  
#2 a=1'b1;b=1'b1;s0=1'b0;  
#2 a=1'b1;b=1'b1;s0=1'b1;  
end
endmodule

```
![WhatsApp Image 2024-04-07 at 22.28.47](https://hackmd.io/_uploads/S19dB8ex0.jpg)
