**LAB 9**
**Question 1**
```verilog=
module alu(res,op,a,b);
input [3:0] a,b;
input [1:0] op;
output reg [3:0] res;
always@(a or b or op or res)
begin
case(op)
2'b00: res = a + b;
2'b01: res = a - b;
2'b10: res = a & b;
2'b11: res = a | b;
default: res = 4'b0000;
endcase
end
endmodule
module mux4to1(out1,in0,in1,in2,in3,sel);
input [3:0] in0,in1,in2,in3;
input [1:0] sel;
output reg [3:0] out1;
always@(in0 or in1 or in2 or in3 or sel)
begin
case(sel)
2'b00: out1 = in0;
2'b01: out1 = in1;
2'b10: out1 = in2;
2'b11: out1 = in3;
default: out1 = 4'b0000;
endcase
end
endmodule
//test bench
module testbench;
reg [3:0] a,b;
reg [1:0] opcode;
wire [3:0] result,out;
alu at(.res(result),.op(opcode),.a(a),.b(b));
mux4to1 m(.out1(out),.in0(4'b0000),.in1(4'b0000),.in2(4'b0000),.in3(result),.sel(opcode));
initial
begin
a = 4'b1100; b = 4'b0011; opcode = 2'b00; #10;
a = 4'b0111; b = 4'b0000; opcode = 2'b01; #10;
a = 4'b0100; b = 4'b1111; opcode = 2'b10; #10;
a = 4'b0010; b = 4'b1001; opcode = 2'b11; #10;
end
endmodule
```

**Question 2**
```verilog=
module processor(input [7:0] inst);
reg [7:0] memory [255:0];
reg [7:0] regf [15:0];
reg op;
reg [1:0] destination;
reg [2:0] offset;
reg [1:0] src;
always@(*)
begin
op = inst[7];
destination = inst[6:5];
offset = inst[4:2];
src = inst[1:0];
end
always@(*)
begin
if(op == 0)
begin
regf[destination] <= memory[regf[src]+offset];
end
end
always@(*)
begin
if(op == 1)
begin
memory[regf[src]+offset] <= regf[destination];
end
end
endmodule
```

**Question 3**
```C=
#include <stdio.h>
int main() {
int a = 5;
int b = 6;
int c = a + b;
printf("c = %d\n", c);
return 0;
}
```
